# US 10,312,093 B2 · Semiconductor device having a surface insulator layer and manufacturing method therefor

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- Number: US 10,312,093 B2
- Document ID: US10312093B2
- Status: Granted
- Kind: B2
- Application number: 15/820,561
- Filed: 2017-11-22
- Published: 2018-09-27
- Granted: 2019-06-04
- Earliest claimed: 2017-03-24
- Assignees: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Applicants: Semiconductor Manufacturing International (Shanghai) Corporation; Semiconductor Manufacturing International (Beijing) Corporation
- Inventors: Xianming Zhang; Ling Tang; Leibin Yuan; Feng Dou; Feng Chen
- Web page: https://patentgrep.com/patent/US10312093B2

## CPC

- H10D 64/513: {within recesses in the substrate, e.g. trench gates, groove gates or buried gates}
- H10D 12/038: {having a recessed gate, e.g. trench-gate IGBTs}
- H10D 12/481: {having gate structures on slanted surfaces, on vertical surfaces, or in grooves, e.g. trench gate IGBTs}
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/252: {for vertical or pseudo-vertical devices}
- H10D 64/258: {characterised by the relative positions of the source or drain electrodes with respect to the gate electrode}
- H10D 64/62: Electrodes ohmically coupled to a semiconductor
- H10D 64/661: {the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon having vertical doping variation (having lateral variation in the gate structure H10D64/671)}
- H10P 14/418: {the conductive layers comprising transition metals}
- H10P 14/6308: {of Group IV semiconductors}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/077: {on sidewalls or on top surfaces of conductors (H10W20/076 takes precedence)}
- H10W 20/082: {the openings being tapered via holes}
- H10W 72/019: {of bond pads}
- H10W 72/552: {comprising metals or metalloids, e.g. silver}
- H10W 72/59: Bond pads specially adapted therefor
- H10W 72/923: {Bond pads having multiple stacked layers}
- H10W 72/934: {Cross-sectional shape, i.e. in side view}
- H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu}
- H10W 72/983: {Reinforcing structures, e.g. collars}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

The present disclosure relates to the technical field of semiconductors, and discloses a semiconductor device and a manufacturing method therefor. The manufacturing method includes: providing a semiconductor structure, where the semiconductor structure includes an active region and a gate structure located in the active region, the gate structure at least including a gate electrode, and the active region exposing an upper surface of the gate electrode; forming a surface insulator layer on the upper surface of the gate electrode; forming a patterned interlayer dielectric layer on the semiconductor structure, where the interlayer dielectric layer covers the surface insulator layer, and has a first through hole exposing a portion of the active region; and forming a conductive contact layer passing through the first through hole and contacting with the active region. The present disclosure may reduce a leakage current which is possibly generated between the conductive contact layer and the gate electrode, so as to improve the performance of the device.

## Claims

### Claim 1

A method for manufacturing a semiconductor device, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises: an active region and a gate structure located in the active region, the gate structure comprising a gate electrode, and the active region exposing an upper surface of the gate electrode;
forming a surface insulator layer on the upper surface of the gate electrode, wherein the surface insulator layer is formed by performing oxidation on the upper surface of the gate electrode;
forming a patterned interlayer dielectric layer on the semiconductor structure, wherein the interlayer dielectric layer covers the surface insulator layer, and has a first through hole exposing a portion of the active region; and
forming a conductive contact layer passing through the first through hole and contacting with the active region.

### Claim 2 (depends on 1)

The method according to claim 1, wherein:
material of the gate electrode comprises polysilicon; and
material of the surface insulator layer comprises an oxide of silicon.

### Claim 3 (depends on 1)

The method according to claim 1, comprising:
oxidizing the upper surface of the gate electrode by performing annealing processing on the upper surface of the gate electrode in an atmosphere of air or oxygen, so as to form the surface insulator layer.

### Claim 4 (depends on 3)

The method according to claim 3, wherein
the annealing processing is a laser annealing processing.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the step of performing the laser annealing processing comprises:
forming a patterned first mask layer on the semiconductor structure, the first mask layer having a first opening exposing the upper surface of the gate electrode; and
in an atmosphere of air or oxygen, irradiating a laser pulse to the upper surface of the gate electrode through the first opening, so as to perform the laser annealing processing, thereby oxidizing the upper surface of the gate electrode; and
removing the first mask layer.

### Claim 6 (depends on 5)

The method according to claim 5, wherein a wavelength range of the laser pulse is between 200 nm and 350 nm.

### Claim 7 (depends on 5)

The method according to claim 5, wherein
a thickness of the surface insulator layer is controlled and adjusted by adjusting at least one of energy or irradiation times of the laser pulse.

### Claim 8 (depends on 1)

The method according to claim 1, wherein
the first through hole is a tapered through hole, the tapered through hole having an upper opening far away from an upper surface of the active region and a lower opening adjacent to the upper surface of the active region, wherein a width of the upper opening is greater than a width of the lower opening.

### Claim 9 (depends on 8)

The method according to claim 8, wherein
an angle range of a side-wall inclination angle of the tapered through hole is from 30° to 40°.

### Claim 10

A method for manufacturing a semiconductor device, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises: an active region and a gate structure located in the active region, the gate structure comprising a gate electrode, and the active region exposing an upper surface of the gate electrode;
forming a surface insulator layer on the upper surface of the gate electrode;
forming a patterned interlayer dielectric layer on the semiconductor structure, wherein the interlayer dielectric layer covers the surface insulator layer, and has a first through hole exposing a portion of the active region; and
forming a conductive contact layer passing through the first through hole and contacting with the active region;
wherein the step of forming a patterned interlayer dielectric layer on the semiconductor structure comprises:
forming an interlayer dielectric layer covering the semiconductor structure;
forming a patterned second mask layer on the interlayer dielectric layer, wherein the second mask layer has a second opening exposing a portion of the interlayer dielectric layer;
performing reflow processing on the second mask layer, so as to reduce a side-wall inclination angle of the second opening;
etching the interlayer dielectric layer using the second mask layer processed with the reflow processing as a mask, so as to form the first through hole; and
removing the second mask layer.

### Claim 11 (depends on 10)

The method according to claim 10, wherein:
a temperature range of the reflow processing is from 100° C. to 300° C.; and
a time range of the reflow processing is from 2 minutes to 5 minutes.

### Claim 12

A method for manufacturing a semiconductor device, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises: an active region and a gate structure located in the active region, the gate structure comprising a gate electrode, and the active region exposing an upper surface of the gate electrode;
forming a surface insulator layer on the upper surface of the gate electrode;
forming a patterned interlayer dielectric layer on the semiconductor structure, wherein the interlayer dielectric layer covers the surface insulator layer, and has a first through hole exposing a portion of the active region; and
forming a conductive contact layer passing through the first through hole and contacting with the active region;
wherein:
in the step of providing a semiconductor structure, the gate structure further comprises a gate insulator layer separating the gate electrode from the active region; and
in the step of forming the surface insulator layer, the surface insulator layer and the gate insulator layer enclose the gate electrode.

### Claim 13

A method for manufacturing a semiconductor device, comprising:
providing a semiconductor structure, wherein the semiconductor structure comprises: an active region and a gate structure located in the active region, the gate structure comprising a gate electrode, and the active region exposing an upper surface of the gate electrode;
forming a surface insulator layer on the upper surface of the gate electrode;
forming a patterned interlayer dielectric layer on the semiconductor structure, wherein the interlayer dielectric layer covers the surface insulator layer, and has a first through hole exposing a portion of the active region;
forming a conductive contact layer passing through the first through hole and contacting with the active region;
forming a patterned passivation layer on the conductive contact layer, the passivation layer having a second through hole exposing a portion of the conductive contact layer; and
forming a metal connector passing through the second through hole and contacting with the conductive contact layer.