# US 10,312,092 B2 · Semiconductor structure and manufacturing method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,312,092 B2
- Document ID: US10312092B2
- Status: Granted
- Kind: B2
- Application number: 15/875,244
- Filed: 2018-01-19
- Published: 2018-05-24
- Granted: 2019-06-04
- Earliest claimed: 2015-03-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Company Ltd.
- Inventors: Ru-Shang Hsiao; Chi-Cherng Jeng; Chih-Mu Huang
- Web page: https://patentgrep.com/patent/US10312092B2

## CPC

- H10D 64/01324: {characterised by the sectional shape, e.g. T or inverted-T}
- H10D 64/01354: {passivation or protection of the electrode, e.g. using re-oxidation}
- H10D 64/518: {characterised by their lengths or sectional shapes}
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor structure includes a first layer having a recessed surface, a metal layer disposed above the first layer, and a second layer disposed above the metal layer and confined by the recessed surface. The second layer includes a first lateral side and a second lateral side. A first thickness of the second layer in a middle portion between the first lateral side and the second lateral side is less than a second thickness of at least one of the first lateral side and the second lateral side of the second layer. The metal layer has a same material across an entire range covered by the second layer.

## Claims

### Claim 1

A semiconductor structure, comprising:
a first layer comprising a recessed surface;
a metal layer disposed above the first layer; and
a second layer disposed above the metal layer and confined by the recessed surface, the second layer comprising a first lateral side and a second lateral side,
wherein a first thickness of the second layer in a middle portion between the first lateral side and the second lateral side is less than a second thickness of at least one of the first lateral side and the second lateral side of the second layer, wherein the metal layer has a same material across an entire range covered by the second layer, and wherein the metal layer comprises a first lateral side, a second lateral side and a middle portion between the first lateral side and the second lateral side, a third thickness of the middle portion of the metal layer being greater than a fourth thickness of the first lateral side of the metal layer and the fourth thickness being greater than a fifth thickness of the second lateral side of the metal layer.

### Claim 2 (depends on 1)

The semiconductor structure according to claim 1, wherein the metal layer comprises at least one of Al, W, WN, TaN, Ru, TiN, W, WN and WCN.

### Claim 3 (depends on 1)

The semiconductor structure according to claim 1, wherein the second layer comprises at least one of aluminum oxides and tungsten oxides.

### Claim 4 (depends on 1)

The semiconductor structure according to claim 1, wherein the fifth thickness may be less than the third thickness by a range of from about 5% to about 90% of the third thickness.

### Claim 5 (depends on 1)

The semiconductor structure according to claim 1, wherein the fifth thickness is between 200 Å and 500 Å.

### Claim 6 (depends on 1)

The semiconductor structure according to claim 1, wherein a first etch rate of the second layer is less than a second etch rate of the metal layer with respect to an etchant.

### Claim 7 (depends on 6)

The semiconductor structure according to claim 6, wherein a ratio of the first etch rate to the second etch rate of the etchant is between about 1/10 and about 1/100.

### Claim 8 (depends on 6)

The semiconductor structure according to claim 6, wherein the etchant comprises at least one of an abrasive, a surfactant, organic KOH, or NH4OH.

### Claim 9 (depends on 1)

The semiconductor structure according to claim 1, wherein the second thickness is greater than the first thickness by a range between about 10% and about 500%.

### Claim 10 (depends on 1)

The semiconductor structure according to claim 1, wherein the second thickness is between 1 Å and 500 Å.

### Claim 11 (depends on 1)

The semiconductor structure according to claim 1, further comprising a spacer comprising a top surface and surrounding a portion of the metal layer and a portion of the second layer.

### Claim 12 (depends on 11)

The semiconductor structure according to claim 11, wherein the top surface of the spacer is substantially coplanar with the top surface of the second layer.

### Claim 13 (depends on 1)

The semiconductor structure according to claim 1, wherein the first layer comprises a high-k dielectric layer.

### Claim 14

A semiconductor structure, comprising:
a metal layer comprising a first lateral side, a second lateral side and a middle portion between the first lateral side and the second lateral side;
an etch-resistant layer disposed above the metal layer, the first lateral side, the middle portion and the second lateral side comprising a same material across an entire range covered by the etch-resistant layer; and
a dielectric layer surrounding the metal layer and the etch-resistant layer, the dielectric layer contacting the metal layer; and
a spacer surrounding a portion of the metal layer and a portion of the etch-resistant layer,
wherein a first thickness of the middle portion is greater than a second thickness of the metal layer at the first lateral side or the second lateral side.

### Claim 15 (depends on 14)

The semiconductor structure according to claim 14, wherein the metal layer comprises at least one of Al, W, WN, TaN, Ru, TiN, W, WN and WCN.

### Claim 16 (depends on 14)

The semiconductor structure according to claim 14, wherein the etch-resistant layer comprises a first lateral side, a second lateral side and a middle portion between the first lateral side and the second lateral side of the etch-resistant layer, and a first thickness summation of the first lateral side of the metal layer and the first lateral side of the etch-resistant layer is substantially equal to a second thickness summation of the second lateral side of the metal layer and the second lateral side of the etch-resistant layer.

### Claim 17 (depends on 14)

The semiconductor structure according to claim 14, wherein the etch-resistant layer comprises a first lateral side, a second lateral side and a middle portion between the first lateral side and the second lateral side of the etch-resistant layer, and a third thickness summation of the first lateral side of the metal layer and the first lateral side of the etch-resistant layer is substantially equal to a fourth thickness summation of the middle portion of the metal layer and the middle portion of the etch-resistant layer.

### Claim 18 (depends on 14)

The semiconductor structure according to claim 14, wherein an upper surface of the metal layer is in contact with a bottom surface of the etch-resistant layer.

### Claim 19

A method of forming a semiconductor structure, comprising:
forming a dummy gate over a substrate, a spacer over a substrate and surrounding the dummy gate, and an interlayer dielectric layer over the dummy gate and the spacer;
performing a planarization operation on the interlayer dielectric layer to expose the spacer;
forming a recess over the substrate by removing the dummy gate;
depositing a dielectric layer on a bottom of the recess;
forming a first layer covering the dielectric layer and sidewalls of the recess, the first layer comprising a recessed surface;
depositing a metal layer above the first layer and confined by the recessed surface; and
forming a second layer from the metal layer by oxidizing at least a portion of the metal layer,
wherein the second layer comprises a first lateral side, a second lateral side and a middle portion between the first lateral side and the second lateral side, and the middle portion has a thickness less than a thickness of at least one of the first lateral side and the second lateral side; and
wherein an entirety of non-oxidized portions of the metal layer comprise a third lateral side, a fourth lateral side and a second middle portion between the third lateral side and the fourth lateral side, and the second middle portion comprises a thickness greater than a thickness of the third lateral side, and the third lateral side is thicker than the fourth lateral side.

### Claim 20 (depends on 19)

The method according to claim 19, further comprising performing a planarization operation on the metal layer prior to forming the second layer.