# US 10,312,089 B1 · Methods for controlling an end-to-end distance in semiconductor device

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- Number: US 10,312,089 B1
- Document ID: US10312089B1
- Status: Granted
- Kind: B1
- Application number: 15/923,072
- Filed: 2018-03-16
- Published: 2019-05-30
- Granted: 2019-06-04
- Earliest claimed: 2017-11-29
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Yu-Lien Huang; Tsai-Chun Li; Huan-Just Lin; Huang-Ming Chen; Yang-Cheng Wu; Cheng-Hua Yang
- Web page: https://patentgrep.com/patent/US10312089B1

## CPC

- H10P 76/4088: {Processes for improving the resolution of the masks}
- G03F 7/2004: {characterised by the use of a particular light source, e.g. fluorescent lamps or deep UV light}
- G03F 7/36: Imagewise removal not covered by groups G03F7/30 - G03F7/34, e.g. using gas streams, using plasma
- H01J 37/32422: {Arrangement for selecting ions or species in the plasma}
- H10D 84/0149: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10D 84/0158: {the components including FinFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10P 50/283: {by chemical means}
- H10P 50/287: {by chemical means}
- H10P 50/73: {using masks for insulating materials}
- H10P 72/0421: {for drying etching}
- H10P 76/2041: {Photolithographic processes}
- H10P 76/4083: {characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10W 20/069: {by forming self-aligned vias or self-aligned contact plugs}
- H10W 20/0698: {Local interconnections}
- H10W 20/083: {the openings being via holes penetrating underlying conductors}
- H01J 37/321: {the radio frequency energy being inductively coupled to the plasma}
- H01J 37/32715: {Workpiece holder}
- H01J 2237/20214: Rotation
- H01J 2237/20228: Mechanical X-Y scanning
- H01J 2237/334: Etching
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)
- H01J: ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS (spark-gaps H01T; electric arc lamps H05B31/00; particle accelerators H05H)
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.

## Claims

### Claim 1

A method of patterning a layer on a substrate, comprising:
forming a first mask layer over the layer;
forming a second mask layer over the first mask layer;
forming a photoresist layer over the second mask layer;
patterning the photoresist layer using a photolithographic process;
etching the second mask layer using the photoresist layer as a mask to form a feature in the second mask layer;
performing an angled etch to modify the feature by increasing a length of the feature without changing a width of the feature; and
etching the first mask layer using the second mask layer as a mask.

### Claim 2 (depends on 1)

The method of claim 1, wherein the photolithographic process is an extreme ultraviolet (EUV) lithographic process.

### Claim 3 (depends on 1)

The method of claim 1, wherein performing the angled etch comprising:
directing an ion beam towards a top surface of the substrate, wherein a plane including the ion beam is parallel to a plane of a sidewall of the feature along the length of the feature.

### Claim 4 (depends on 3)

The method of claim 3, wherein the ion beam is at an impinging angle relative to a z-axis perpendicular to the top surface of the substrate.

### Claim 5 (depends on 4)

The method of claim 4, wherein the impinging angle is between about 10 degrees to about 30 degrees.

### Claim 6 (depends on 3)

The method of claim 3, wherein the ion beam is a ribbon of ion beam covering a width of the substrate.

### Claim 7 (depends on 3)

The method of claim 3, wherein the ion beam is a bulk ion beam covering the entire top surface of the substrate.

### Claim 8 (depends on 1)

The method of claim 1, wherein the length of the feature is increased by about 20 nm to about 30 nm.

### Claim 9 (depends on 1)

The method of claim 1, wherein the layer is one of an interlayer dielectric layer formed over FinFET device structures.

### Claim 10

A method of forming a semiconductor device, comprising:
forming an interlayer dielectric layer over gate structures of a FinFET structure; and
patterning the interlayer dielectric layer to form a contact opening in the interlayer dielectric layer, comprising:
patterning a hard mask layer over the interlayer dielectric layer to form a first pattern in the hard mask layer, wherein the first pattern includes two or more unidirectional features aligned along a line having an end-to-end distance at a first value; and
performing an angled etch process to increase a length of the two or more unidirectional features without changing a width of the two or more unidirectional features, thereby, reducing the end-to-end distance from the first value to a second value.

### Claim 11 (depends on 10)

The method of claim 10, wherein performing the angled etch process comprises:
directing an ion beam towards a top surface of the interlayer dielectric layer, wherein a plane including the ion beam is parallel to a plane of a sidewall of the two or more unidirectional features along the length of the two or more unidirectional features.

### Claim 12 (depends on 11)

The method of claim 11, wherein the ion beam at an impinging angle relative to a z-axis perpendicular to the top surface of the interlayer dielectric layer.

### Claim 13 (depends on 12)

The method of claim 12, wherein the impinging angle is between about 10 degrees to about 30 degrees.

### Claim 14 (depends on 12)

The method of claim 12, further comprising selecting the impinging angle according to an aspect ratio of the two or more unidirectional features.

### Claim 15 (depends on 10)

The method of claim 10, wherein the length of the two or more unidirectional features is increased by about 20 nm to about 30 nm.

### Claim 16 (depends on 10)

The method of claim 10, wherein patterning the hard mask layer is performed by an extreme ultraviolet (EUV) lithographic process.

### Claim 17 (depends on 10)

The method of claim 10, further comprising:
removing a photoresist layer used in patterning the hard mask layer after performing the angled etch process.

### Claim 18

A method for manufacturing a semiconductor device, comprising:
forming a first pattern in a photoresist layer, wherein the first pattern includes unidirectional features;
etching a mask layer below the photoresist layer using the photoresist layer as a mask to the first pattern in the mask layer; and
directing an ion beam at an angle to increase lengths of the unidirectional features without enlarging a width of the unidirectional features.

### Claim 19

The method of 18, wherein the ion beam is directed along a plane parallel to a plane of sidewalls of the unidirectional features along the length of the unidirectional features.

### Claim 20 (depends on 18)

The method of claim 18, wherein forming the first pattern in a photoresist layer is performed by an extreme ultraviolet (EUV) lithographic process.