# US 10,312,085 B2 · Tone inversion integration for phase change memory

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- Number: US 10,312,085 B2
- Document ID: US10312085B2
- Status: Granted
- Kind: B2
- Application number: 16/045,788
- Filed: 2018-07-26
- Published: 2019-05-09
- Granted: 2019-06-04
- Earliest claimed: 2017-11-03
- Assignees: International Business Machines Corporation
- Applicants: International Business Machines Corporation
- Inventors: Matthew J. BrightSky; Robert L. Bruce; John M. Papalia; HsinYu Tsai
- Web page: https://patentgrep.com/patent/US10312085B2

## CPC

- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/061: {Shaping switching materials}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/841: {Electrodes}
- H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- H10P 14/2919: {being chalcogenide semiconducting materials not being oxides, e.g. ternary compounds}
- H10P 14/3236: {being chalcogenide semiconducting materials not being oxides, e.g. ternary compounds}
- H10P 14/3436: {being chalcogenide semiconductor materials not being oxides, e.g. ternary compounds}
- H10P 50/73: {using masks for insulating materials}
- H10W 20/089: {using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

Embodiments of the invention are directed to methods and resulting structures for forming a storage element using phase change memory (PCM). In a non-limiting embodiment of the invention, a PCM layer is formed over a surface of a bottom electrode. A top electrode is formed over the PCM layer using a tone inversion process that includes a sacrificial layer. A PCM pillar is then formed by patterning the PCM layer to expose a surface of the bottom electrode. The tone inversion process enables a sub-50 nm PCM pillar diameter.

## Claims

### Claim 1

A semiconductor device comprising:
a bottom electrode
a phase change memory (PCM) pillar formed over a surface of the bottom electrode;
an etch stop layer formed over the PCM pillar; and
a ring electrode formed over the etch stop layer, the ring electrode comprising three stacked electrode layers;
wherein the PCM pillar comprises a diameter of about 10 nm to about 50 nm.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the PCM pillar comprises a germanium-antimony-tellurium (GST) ternary compound.

### Claim 3 (depends on 1)

The semiconductor device of claim 1, wherein the bottom electrode is electrically isolated between two portions of a dielectric layer.