# US 10,312,084 B2 · Semiconductor device and fabrication method thereof

> Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt

- Number: US 10,312,084 B2
- Document ID: US10312084B2
- Status: Granted
- Kind: B2
- Application number: 15/439,890
- Filed: 2017-02-22
- Published: 2017-06-08
- Granted: 2019-06-04
- Earliest claimed: 2015-11-20
- Assignees: United Microelectronics Corp.
- Applicants: United Microelectronics Corp.
- Inventors: Kuang-Hsiu Chen; Yi-Liang Ye; Chueh-Yang Liu; Yu-Ren Wang
- Web page: https://patentgrep.com/patent/US10312084B2

## CPC

- H10P 76/4083: {characterised by their behaviours during the lithography processes, e.g. soluble masks or redeposited masks}
- H10D 30/0227: {having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET}
- H10D 30/601: {having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs (lightly doped source or drain extensions for TFTs H10D30/6715)}
- H10D 30/797: {being in source or drain regions, e.g. SiGe source or drain}
- H10D 62/021: {Forming source or drain recesses by etching e.g. recessing by etching and then refilling}
- H10D 62/151: {of IGFETs (of IGFETs having LDD or DDD structure H10D30/601; of thin film transistors H10D30/6713)}
- H10D 62/80: characterised by the materials
- H10D 62/82: Heterojunctions
- H10D 64/017: {using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes}
- H10D 64/021: {using multiple gate spacer layers, e.g. bilayered sidewall spacers}
- H10D 64/691: {comprising metallic compounds, e.g. metal oxides or metal silicates (insulators comprising nitrogen H10D64/693)}
- H10D 64/693: {the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials}
- H10D 84/017: {Manufacturing their source or drain regions, e.g. silicided source or drain regions}
- H10D 84/0184: {Manufacturing their gate sidewall spacers}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- H10P 14/3402: {characterised by the chemical composition}
- H10P 30/204: {into Group IV semiconductors}
- H10P 30/21: {of electrically active species}
- H10P 76/405: {characterised by their composition, e.g. multilayer masks}
- H10P 76/4085: {characterised by the processes involved to create the masks}
- H10P 95/00: Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
- H10D 64/667: {the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671)}
- H10D 84/0186: {Manufacturing their interconnections or electrodes, e.g. source or drain electrodes}
- H10P: GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A method for fabricating the semiconductor device is disclosed. A semiconductor substrate having a main surface is provided. A gate is formed on the main surface of the semiconductor substrate. An offset liner is formed on the sidewall of the gate. An ion implantation process is performed to form lightly doped drain (LDD) region in the semiconductor substrate. A spacer is formed on a sidewall of the gate. A cavity is recessed into the main surface of the semiconductor substrate. The cavity is adjacent to the spacer. An epitaxial layer is grown in the cavity. The spacer is then subjected to a surface treatment to form a dense oxide film on the spacer. A mask layer is deposited on the dense oxide film. The dense oxide film has a thickness that is smaller or equal to 12 angstroms.

## Claims

### Claim 1

A method for fabricating a semiconductor device, comprising:
providing a semiconductor substrate having a main surface;
forming a gate on the main surface of the semiconductor substrate;
forming a spacer on a sidewall of the gate;
forming a cavity recessed into the main surface of the semiconductor substrate, wherein the cavity is adjacent to the spacer;
growing an epitaxial layer in the cavity;
after growing the epitaxial layer in the cavity, forming a densified silicon oxide film on the spacer; and
depositing a mask layer on the densified silicon oxide film.

### Claim 2 (depends on 1)

The method for fabricating a semiconductor device of claim 1, wherein the gate is a polysilicon gate.

### Claim 3 (depends on 1)

The method for fabricating a semiconductor device of claim 1, wherein before forming the spacer, the method further comprises:
forming an offset liner on the sidewall of the gate; and
performing an ion implantation process to form lightly doped drain (LDD) region in the semiconductor substrate.

### Claim 4 (depends on 3)

The method for fabricating a semiconductor device of claim 3, wherein the offset liner comprises carbon and nitrogen doped silicon oxide.

### Claim 5 (depends on 4)

The method for fabricating a semiconductor device of claim 4, wherein the spacer comprises carbon and nitrogen doped silicon oxide.

### Claim 6 (depends on 1)

The method for fabricating a semiconductor device of claim 1, wherein the said forming a densified silicon oxide film on the spacer comprises:
contacting the spacer with diluted HF;
contacting the spacer with sulfuric acid and hydrogen peroxide mixture (SPM) solution; and
contacting the spacer with ozone water.

### Claim 7 (depends on 1)

The method for fabricating a semiconductor device of claim 1, wherein the densified silicon oxide film has a thickness that is smaller or equal to 12 angstroms.

### Claim 8 (depends on 1)

The method for fabricating a semiconductor device of claim 1, wherein the mask layer comprises silicon-rich silicon nitride.