# US 10,312,072 B2 · Structure for FinFET devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,312,072 B2 - Document ID: US10312072B2 - Status: Granted - Kind: B2 - Application number: 16/045,576 - Filed: 2018-07-25 - Published: 2018-12-06 - Granted: 2019-06-04 - Earliest claimed: 2017-05-31 - Assignees: Taiwan Semiconductor Manufacturing Company, Ltd. - Applicants: Taiwan Semiconductor Manufacturing Co., Ltd. - Inventors: Jin Cai - Web page: https://patentgrep.com/patent/US10312072B2 ## CPC - H10D 84/834: {comprising FinFETs} - H10D 30/024: {of fin field-effect transistors [FinFET]} - H10D 30/6211: {having fin-shaped semiconductor bodies integral with the bulk semiconductor substrates} - H10D 84/0193: {the components including FinFETs} - H10D 84/038: {using silicon technology, e.g. SiGe} - H10D 84/853: {comprising FinFETs} - H10H 20/062: {Light-emitting semiconductor devices having field effect type light-emitting regions, e.g. light-emitting High-Electron Mobility Transistors} - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES - H10H: INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS ## Abstract A semiconductor device and a method of forming the same are disclosed. The semiconductor device includes a semiconductor substrate; a fin extending from the semiconductor substrate; a first charged dielectric layer covering a bottom portion of the fin, the first charged dielectric layer having net fixed first-type charges; a second charged dielectric layer covering the first charged dielectric layer, the second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges; and a gate structure engaging a top portion of the fin. ## Claims ### Claim 1 A semiconductor device, comprising: a semiconductor substrate; a fin extending from the semiconductor substrate; a first charged dielectric layer covering a bottom portion of the fin, the first charged dielectric layer having net fixed first-type charges; a second charged dielectric layer covering the first charged dielectric layer, the second charged dielectric layer having net fixed second-type charges, the second-type charges being opposite to the first-type charges; a spacer layer conformal to the fin, the spacer layer being interposed between the first charged dielectric layer and the second charged dielectric layer, the spacer layer being electric neutral; and a gate structure engaging a top portion of the fin. ### Claim 2 (depends on 1) The semiconductor device of claim 1, wherein the first charged dielectric layer and the second charged dielectric layer are both conformal to the fin. ### Claim 3 (depends on 1) The semiconductor device of claim 1, wherein the spacer layer contains a composition selected from silicon oxynitride, silicon carbide nitride, silicon oxide carbide nitride, and a combination thereof. ### Claim 4 (depends on 1) The semiconductor device of claim 1, wherein the first-type charges has a first sheet density and the second-type charges has a second sheet density, the first sheet density being higher than the second sheet density. ### Claim 5 (depends on 4) The semiconductor device of claim 4, wherein: the first sheet density is within a range of 2×1011/cm2 to 1×1013/cm2; and the second sheet density is within a range of 2×1011/cm2 to 1×1013/cm2. ### Claim 6 (depends on 1) The semiconductor device of claim 1, wherein: the top portion of the fin provides a channel for an n-type field effect transistor; the first-type charges are negative charges; and the second-type charges are positive charges. ### Claim 7 (depends on 6) The semiconductor device of claim 6, wherein the first charged dielectric layer contains aluminum oxide and the second charged dielectric layer contains silicon nitride. ### Claim 8 (depends on 1) The semiconductor device of claim 1, further comprising: an isolation feature covering and in direct contact with the second charged dielectric layer. ### Claim 9 (depends on 8) The semiconductor device of claim 8, wherein the isolation feature is a shallow trench isolation (STI) feature. ### Claim 10 A semiconductor device, comprising: a semiconductor substrate having a first region and a second region; a first fin extending from the semiconductor substrate within the first region; a first dielectric layer surrounding a bottom portion of the first fin, the first dielectric layer being within the first region; a second fin extending from the semiconductor substrate within the second region; a second dielectric layer surrounding a bottom portion of the second fin, a portion of the second dielectric layer extending into the first region and covering at least a portion of the first dielectric layer; and a spacer layer within the first region, the spacer layer being interposed between the first dielectric layer and the portion of the second dielectric layer extending into the first region, wherein the spacer layer is electric neutral, and wherein the first dielectric layer contains fixed first-type charges and the second dielectric layer contains fixed second-type charges opposite to the first-type charges. ### Claim 11 (depends on 10) The semiconductor device of claim 10, wherein the first dielectric layer has a thickness larger than the second dielectric layer. ### Claim 12 (depends on 10) The semiconductor device of claim 10, wherein the first dielectric layer has a sheet charge carrier density higher than the second dielectric layer. ### Claim 13 (depends on 10) The semiconductor device of claim 10, wherein the fixed first-type charges are fixed negative charges and the fixed second-type charges are fixed positive charges. ### Claim 14 (depends on 10) The semiconductor device of claim 10, wherein the first dielectric layer includes aluminum oxide and the second dielectric layer includes silicon nitride. ### Claim 15 A semiconductor device, comprising: a substrate; an isolation structure over the substrate; a first fin extending from the substrate, wherein a first portion of the first fin is above the isolation structure and a second portion of the first fin is surrounded by the isolation structure; a first dielectric layer between the isolation structure and the second portion of the first fin, wherein the first dielectric layer contains fixed first-type charges; a second fin extending from the substrate, wherein a first portion of the second fin is above the isolation structure and a second portion of the second fin is surrounded by the isolation structure; and a second dielectric layer between the isolation structure and the second portion of the second fin, wherein the second dielectric layer contains fixed second-type charges, wherein the first-type charges are opposite to the second-type charges, and wherein the first portion of the first fin includes a p-type doped channel for an n-type field effect transistor and the first-type charges are negative charges, and wherein the first portion of the second fin includes an n-type doped channel for a p-type field effect transistor and the second-type charges are positive charges. ### Claim 16 (depends on 15) The semiconductor device of claim 15, wherein: the first dielectric layer contains aluminum oxide; and the second dielectric layer contains silicon nitride. ### Claim 17 (depends on 15) The semiconductor device of claim 15, wherein: the first dielectric layer has a sheet charge carrier density within a range of 2×1011/cm2 to 1×1013/cm2; and the second dielectric layer has a sheet charge carrier density within a range of 2×1011/cm2 to 1×1013/cm2. ### Claim 18 (depends on 15) The semiconductor device of claim 15, wherein the isolation structure is a shallow trench isolation (STI) feature. ### Claim 19 (depends on 15) The semiconductor device of claim 15, wherein the second dielectric layer extends to the first dielectric layer such that the second dielectric layer covers a top surface of the first dielectric layer, the top surface of the dielectric layer facing away from the substrate. ### Claim 20 (depends on 19) The semiconductor device of claim 19, further comprising a spacer layer interposed between the first dielectric layer and the second dielectric layer, the spacer layer being electric neutral.