# US 10,311,966 B2 · On-chip diagnostic circuitry monitoring multiple cycles of signal samples > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,966 B2 - Document ID: US10311966B2 - Status: Granted - Kind: B2 - Application number: 15/050,169 - Filed: 2016-02-22 - Published: 2017-08-24 - Granted: 2019-06-04 - Earliest claimed: 2016-02-22 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Anthony G. Aipperspach; Derick G. Behrends; Todd A. Christensen; Jeffrey M. Scherer - Web page: https://patentgrep.com/patent/US10311966B2 ## CPC - G11C 29/56016: {Apparatus features} - G11C 29/02: Detection or location of defective auxiliary circuits, e.g. defective refresh counters - G11C 29/022: {in I/O circuitry} - G11C 29/023: {in clock generator or timing circuitry} - G11C 29/025: {in signal lines} - G11C 29/12005: {comprising voltage or current generators} - G11C 29/1201: {comprising I/O circuitry} - G11C 29/46: Test trigger logic - G01R 31/3187: Built-in tests - G11C 2029/1208: {Error catch memory} - G11C 2029/5602: {Interface to device under test} - G11C: STATIC STORES (semiconductor memory devices H10B) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A system and integrated circuits are provided for determining performance metrics over a plurality of cycles of an input signal using on-chip diagnostic circuitry. The system comprises a trigger generation module configured to generate a trigger signal, and diagnostic circuitry coupled with the trigger generation module. The diagnostic circuitry comprises a memory comprising a plurality of data lines, and a plurality of delay elements, each delay element of the plurality of delay elements connected between consecutive data lines of the plurality of data lines. The diagnostic circuitry is configured to receive at least one input signal, and write, upon receiving the trigger signal, values on the plurality of data lines to the memory, thereby acquiring samples of a plurality of cycles of the input signal. ## Claims ### Claim 1 A system, comprising: a trigger generation module configured to generate a trigger signal; and diagnostic circuitry coupled with the trigger generation module, the diagnostic circuitry comprising: a fast-switching circuit configured to receive an input signal and produce a first output signal indicating transition in the input signal in response to the input signal exceeding a first voltage threshold; a slow-switching circuit configured to receive the input signal and produce a second output signal indicating the transitions in the input signal with a delay compared to the first output signal in response to the input signal exceeding a second voltage threshold greater than the first voltage threshold; and an exclusive-OR (XOR) gate configured to receive the first and second output signals and to generate a slew rate signal; a memory comprising a plurality of data lines and a plurality of address lines; and a plurality of delay elements, each delay element of the plurality of delay elements connected between consecutive data lines of the plurality of data lines, wherein the diagnostic circuitry is configured to: receive the slew rate signal on the plurality of data lines; and write, upon receiving the trigger signal, values of the slew rate signal carried on the plurality of data lines to at least one address line of the plurality of address lines, thereby acquiring samples of a plurality of cycles of the slew rate signal. ### Claim 2 (depends on 1) The system of claim 1, wherein the diagnostic circuitry further comprises a counter, wherein writing values on the plurality of data lines to the at least one address line of the plurality of address lines comprises: writing a first plurality of samples of the slew rate signal to a first address line of the plurality of address lines, the first address line indicated by an initial value of the counter; and writing, after incrementing the initial value of the counter, a second plurality of samples of the slew rate signal to a second address line of the plurality of address lines, the second address line indicated by the incremented value. ### Claim 3 (depends on 2) The system of claim 2, wherein the diagnostic circuitry is further configured to combine address information included in the generated trigger signal with the initial value of the counter to select the first address line. ### Claim 4 (depends on 2) The system of claim 2, wherein the diagnostic circuitry is configured to acquire samples of a first cycle of the slew rate signal with the first plurality of samples of the slew rate signal, and to acquire samples of a second cycle of the slew rate signal with the second plurality of samples of the slew rate signal. ### Claim 5 (depends on 1) The system of claim 1, wherein the diagnostic circuitry is included on an integrated circuit, the system further comprising an event detection module configured to: determine when one or more predetermined operational conditions of the integrated circuit are met during operation of the integrated circuit; and instruct the trigger generation module to generate the trigger signal, thereby signaling the diagnostic circuitry to begin operation. ### Claim 6 (depends on 5) The system of claim 5, wherein the samples of a plurality of cycles of the slew rate signal acquired by the diagnostic circuitry are subsequently associated with the determined one or more predetermined operational conditions and used to dynamically adjust operation of the integrated circuit. ### Claim 7 (depends on 5) The system of claim 5, wherein the diagnostic circuitry further comprises a multiplexer configured to receive a plurality of input signals and configured to receive a select signal to select one of the plurality of input signals, wherein the select signal is based on the determined one or more predetermined operational conditions of the integrated circuit. ### Claim 8 (depends on 1) The system of claim 1, wherein the diagnostic circuitry is configured to determine, based on the acquired samples of a plurality of cycles of the slew rate signal, one or more of a duty cycle and a slew rate of the input signal. ### Claim 9 (depends on 1) The system of claim 1, wherein the first output signal and the second output signal are different from the input signal. ### Claim 10 An integrated circuit comprising: a plurality of internal nets, each carrying a respective one of a plurality of signals; and diagnostic circuitry coupled with at least one of the plurality of internal nets, the diagnostic circuitry comprising: slew rate diagnostic circuitry configured to generate, based on a selected signal of the plurality of signals, a slew rate signal comprising a pulse having a pulse width, the pulse width indicating a slew rate of the selected signal, wherein the slew rate diagnostic circuitry includes: a fast-switching circuitry configured to receive the selected signal and produce a first output signal indicating transitions in the selected signal in response to the selected signal exceeding a first voltage threshold; slow-switching circuitry configured to receive the selected signal and produce a second output signal indicating the transitions in the selected signal with a delay compared to the first output signal in response to the selected signal exceeding a second voltage threshold greater than the first voltage threshold; and an exclusive-OR (XOR) gate configured to receive the first and second output signals and to generate the slew rate signal; a memory comprising a plurality of data lines and a plurality of address lines; and a plurality of delay elements, each delay element of the plurality of delay elements connected between consecutive data lines of the plurality of data lines, wherein the diagnostic circuitry is configured to write, upon receiving a trigger signal, values on the plurality of data lines to the plurality of address lines, thereby acquiring a plurality of samples of the slew rate signal corresponding to a plurality of transitions of the selected signal. ### Claim 11 (depends on 10) The integrated circuit of claim 10, wherein the diagnostic circuitry further comprises a counter, wherein writing values on the plurality of data lines to the plurality of address lines comprises: writing a first plurality of samples of the slew rate signal to a first address line of the plurality of address lines, the first address line indicated by an initial value of the counter; and writing, after incrementing the initial value of the counter, a second plurality of samples of the slew rate signal to a second address line of the plurality of address lines, the second address line indicated by the incremented value. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein the diagnostic circuitry is further configured to combine address information included in the received trigger signal with the initial value of the counter to select the first address line. ### Claim 13 (depends on 11) The integrated circuit of claim 11, wherein the diagnostic circuitry is configured to: acquire, at the first address line, a first plurality of samples of the slew rate signal corresponding to a first transition of the selected signal, and acquire, at the second address line, a second plurality of samples of the slew rate signal corresponding to a second transition of the selected signal. ### Claim 14 (depends on 10) The integrated circuit of claim 10, further comprising a trigger generation module configured to: generate the trigger signal responsive to determining one or more predetermined operational conditions of the integrated circuit are met, thereby signaling the diagnostic circuitry to begin operation. ### Claim 15 (depends on 14) The integrated circuit of claim 14, wherein the plurality of samples of the slew rate signal acquired by the diagnostic circuitry are subsequently associated with the determined one or more predetermined operational conditions and used to dynamically adjust operation of the integrated circuit. ### Claim 16 (depends on 10) The integrated circuit of claim 10, wherein the fast-switching circuitry is configured to detect a beginning of a transition of the selected signal, and wherein the slow-switching circuitry is configured to detect an ending of the transition of the selected signal. ### Claim 17 (depends on 10) The integrated circuit of claim 10, wherein the first output signal and the second output signal are different from the selected signal. ### Claim 18 An integrated circuit comprising: a plurality of internal nets each carrying a respective one of a plurality of signals; a fast-switching circuit configured to receive a selected signal of the plurality of signals and to produce a first output signal in response to the selected signal transitioning above a first voltage threshold as a first transition indicator; a slow-switching circuit configured to receive the selected signal and to produce a second output signal in response to the selected signal above a second voltage threshold that is higher than first voltage threshold as a second transition indicator; a pulse generating circuit configured to generate a pulse based on the first and second transition indicators; and diagnostic circuitry comprising a memory having a plurality of data lines and a plurality of address lines, wherein the diagnostic circuitry is configured to acquire a plurality of samples of the generated pulse in the memory. ### Claim 19 (depends on 18) The integrated circuit of claim 18, wherein the diagnostic circuitry further comprises a plurality of delay elements, each delay element of the plurality of delay elements connected between consecutive data lines of the plurality of data lines. ### Claim 20 (depends on 18) The integrated circuit of claim 18, wherein the diagnostic circuitry further comprises a counter, wherein acquiring a plurality of samples of the generated pulse in the memory comprises: writing a first plurality of samples of a first generated pulse to a first address line of the plurality of address lines, the first generated pulse corresponding to a first transition of the selected signal, the first address line indicated by an initial value of the counter; writing, after incrementing the initial value of the counter, a second plurality of samples of a second generated pulse to a second address line of the plurality of address lines, the second generated pulse corresponding to a second transition of the selected signal, the second address line indicated by the incremented value.