# US 10,311,963 B2 · Data processing > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,963 B2 - Document ID: US10311963B2 - Status: Granted - Kind: B2 - Application number: 15/491,239 - Filed: 2017-04-19 - Published: 2018-10-25 - Granted: 2019-06-04 - Earliest claimed: 2017-04-19 - Assignees: Arm Limited - Applicants: Arm Limited - Inventors: Mark Gerald LaVine; Alan Jeremy Becker - Web page: https://patentgrep.com/patent/US10311963B2 ## CPC - G11C 29/12: Built-in arrangements for testing, e.g. built-in self testing [BIST] {or interconnection details} - G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits} - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 8/10: Decoders - G11C 29/38: Response verification devices - G11C 29/44: Indication or identification of errors, e.g. for repair - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 2029/0409: {Online test} - G11C 2029/0411: {Online error correction} - G11C 2029/1208: {Error catch memory} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A data processing apparatus comprises at least one memory configured to store data; processing circuitry to access data in the at least one memory. Memory built-in self-test (MBIST) circuitry has an interface to access the at least one memory and is configured to perform a test procedure for testing at least one target memory location of the at least one memory. The test procedure involves at least writing test data to the target memory location. Diagnostic circuitry executes a diagnostic procedure to generate diagnostic data in response to processing operations carried out by the processing circuitry. The MBIST circuitry is configured to control writing of the diagnostic data generated by the diagnostic circuitry to memory locations in a temporarily reserved memory region comprising at least a portion of the at least one memory. ## Claims ### Claim 1 A data processing apparatus comprising: at least one memory configured to store data, the at least one memory comprising a cache memory; processing circuitry to access data in the at least one memory; memory built-in self-test (MBIST) circuitry having an interface to access the at least one memory and being configured to perform a test procedure for testing at least one target memory location of the at least one memory, the test procedure comprising at least writing test data to the target memory location; diagnostic circuitry to execute a diagnostic procedure to generate diagnostic data in response to processing operations carried out by the processing circuitry; a cache controller to control data storage to, and data retrieval from, the cache memory; and control circuitry to reserve a memory region comprising at least a portion of the at least one memory, to store the diagnostic data generated by the diagnostic circuitry executing the diagnostic procedure; wherein: the MBIST circuitry is configured to control writing of the diagnostic data generated by the diagnostic circuitry to memory locations in a temporarily reserved memory region comprising at least a portion of the at least one memory; the cache controller is configured to allocate portions of the cache memory for temporary storage of data corresponding to addresses in a higher level memory; and the control circuitry is configured to reserve a memory region of the cache memory by indicating to the cache controller that the temporarily reserved memory region is unavailable for allocation by the cache controller. ### Claim 2 (depends on 1) Apparatus according to claim 1, in which the MBIST circuitry is configured to execute a memory read procedure to retrieve data stored in the temporarily reserved memory region and to provide the retrieved data to an external interface. ### Claim 3 (depends on 2) Apparatus according to claim 2, in which the at least one memory is configured to continue allowing access by the processing circuitry to memory locations other than memory locations in the temporarily reserved memory region. ### Claim 4 (depends on 2) Apparatus according to claim 2 in which the control circuitry is configured to release the temporarily reserved memory region following completion of the memory read procedure in respect of the temporarily reserved memory region. ### Claim 5 (depends on 1) Apparatus according to claim 1, in which: the portions of the cache memory comprise cache lines or ways each storing data corresponding to a contiguous range of addresses in the higher level memory; and the control circuitry is configured to reserve one or more cache lines or ways. ### Claim 6 (depends on 1) Apparatus according to claim 1, comprising a plurality of memories, in which the control circuitry is configured to select a memory, of the plurality of memories, in which to reserve a memory region. ### Claim 7 (depends on 6) Apparatus according to claim 6, in which, for the storage of diagnostic data dependent upon processing operations by the processing circuitry relating to a subset of the plurality of memories, the control circuitry is configured to select one or more memories of the plurality of memories other than the subset of the plurality of memories. ### Claim 8 (depends on 7) Apparatus according to claim 7, comprising a plurality of types of memories. ### Claim 9 (depends on 8) Apparatus according to claim 8, wherein the plurality of types of memories comprise two or more of: a data cache; a snoop filter memory; a level 2 cache memory; a level 3 cache memory; an instruction cache; a graphics data memory; a data tightly coupled memory; a buffer for branch prediction; a buffer for branch targets; a buffer for address translation; and an instruction tightly coupled memory. ### Claim 10 (depends on 6) Apparatus according to claim 6, comprising a plurality of MBIST circuitries, the diagnostic circuitry being connected to the plurality of MBIST circuitries by bus circuitry. ### Claim 11 (depends on 1) Apparatus according to claim 1, in which the control circuitry is configured to provide location information to the MBIST circuitry indicating one or more memory locations in the temporarily reserved memory region. ### Claim 12 (depends on 1) Apparatus according to claim 1, in which the MBIST circuitry is configured to control writing of the diagnostic data to the temporarily reserved memory region according to an order of memory addresses, the order of memory addresses restarting in response to the temporarily reserved memory region being full of the diagnostic data. ### Claim 13 (depends on 2) Apparatus according to claim 2, comprising a debug apparatus connected to the external interface to receive the retrieved data. ### Claim 14 A data processing apparatus comprising: at least one memory means for storing data; processing means to access data in the at least one memory means, the at least one memory means comprising a cache memory means; memory built-in self-test (MBIST) means having an interface means for accessing the at least one memory and being configured to perform a test procedure for testing at least one target memory location of the at least one memory, the test procedure comprising at least writing test data to the target memory location; and diagnostic means for executing a diagnostic procedure to generate diagnostic data in response to processing operations carried out by the processing means; cache controller means for controlling the storage of data to, and the retrieval of data from, the cache memory means; and control means for reserving a memory region comprising at least a portion of the at least one memory means, to store the diagnostic data generated by the diagnostic circuitry executing the diagnostic procedure; wherein: the MBIST means is configured to control writing of the diagnostic data generated by the diagnostic means to memory locations in a temporarily reserved memory region comprising at least a portion of the at least one memory means; the cache controller means is operable to allocate portions of the cache memory means for temporary storage of data corresponding to addresses in a higher level memory; and the control means is operable to reserve a memory region of the cache memory means by indicating to the cache controller means that the temporarily reserved memory region is unavailable for allocation by the cache controller means. ### Claim 15 A data processing method comprising: providing memory built-in self-test (MBIST) circuitry having an interface to a cache memory to execute a test procedure for testing at least one target memory location of the cache memory, the MBIST test procedure comprising at least writing test data to the target memory location; controlling, using a cache controller, the storage of data to, and the retrieval of data from, the cache memory; the cache controller allocating portions of the cache memory for temporary storage of data corresponding to addresses in a higher level memory; temporarily reserving a memory region comprising at least a portion of the at least one memory; executing a diagnostic procedure to generate diagnostic data in response to processing operations; and the MBIST circuitry controlling writing of the diagnostic data generated by the executing step to memory locations in a memory region reserved by the temporarily reserving step; the reserving step comprising indicating to the cache controller that the memory region reserved by the temporarily reserving step is unavailable for allocation by the cache controller.