# US 10,311,959 B2 · Voltage degradation aware NAND array management > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,959 B2 - Document ID: US10311959B2 - Status: Granted - Kind: B2 - Application number: 16/130,663 - Filed: 2018-09-13 - Published: 2019-02-28 - Granted: 2019-06-04 - Earliest claimed: 2017-08-31 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Sebastien Andre Jean; Harish Reddy Singidi - Web page: https://patentgrep.com/patent/US10311959B2 ## CPC - G11C 16/3431: {Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step} - G06F 13/16: for access to memory bus (G06F13/28 takes precedence) - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/10: Programming or data input circuits - G11C 16/26: Sensing or reading circuits; Data output circuits - G11C 16/30: Power supply circuits - G11C 16/349: {Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract Devices and techniques for voltage degradation aware NAND array management are disclosed herein. Voltage to a NAND device is monitored to detect a voltage event. A history of voltage events is modified with the voltage event. A voltage condition is observed from the history of voltage events. An operational parameter of a NAND array in the NAND device is then modified in response to the voltage condition. ## Claims ### Claim 1 A memory device for voltage degradation aware memory array management, the memory device comprising: a memory array; and a controller to: detect a variation of a supply voltage to the memory array, the variation determined to be at least one of a threshold drop in supply voltage from an expected supply voltage or a difference in supply voltage between measurements of the supply voltage; record the variation of the supply voltage with other detected variations of the supply voltage to create a voltage event history, the voltage event history being a data structure managed by a controller of the memory device; and change operation of the memory array in response to a metric of voltage variations derived from the voltage event history, the metric of voltage variations measuring a deviation of the supply voltage from a supply voltage for reliable memory array write operations. ### Claim 2 (depends on 1) The memory device of claim 1, wherein, to record the variation of the supply voltage with the other detected variations of the supply voltage, the controller is arranged to change a counter to aggregate the variation of the supply voltage with the other detected variations of the supply voltage. ### Claim 3 (depends on 2) The memory device of claim 2, wherein the counter is changed in a first direction when the supply voltage is greater than a previous measurement, the counter is changed in a second direction when the supply voltage is less than a previous measurement, and the counter is unchanged otherwise. ### Claim 4 (depends on 2) The memory device of claim 2, wherein the counter includes a time-based modification such that the counter is an aggregation of only those measurements that are within a time-window to produce a rate of supply voltage variations. ### Claim 5 (depends on 1) The memory device of claim 1, wherein, to change the operation of the memory array, the controller is arranged to change a write procedure to account for a lower voltage to the memory array. ### Claim 6 (depends on 5) The memory device of claim 5, wherein the write procedure is changed such that data being written is kept in a write buffer after the data is written to the memory array until the data written to the memory array is verified as being correctly written. ### Claim 7 (depends on 6) The memory device of claim 6, wherein a verification that the data is correctly written includes a read of the data from the memory array and comparing a result of the read to the data in the write buffer, the data being correctly written when the result of the read and the data in the write buffer match. ### Claim 8 (depends on 1) The memory device of claim 1, wherein, to change the operation of the memory array, the controller is arranged to modify an error handling procedure of the memory array. ### Claim 9 (depends on 8) The memory device of claim 8, wherein a read-retry error handling procedure is modified by being initiated earlier to recover read data when the supply voltage is low according to the metric of voltage variations. ### Claim 10 (depends on 8) The memory device of claim 8, wherein a program-erase error handling procedure is modified to include additional tests to ensure that charge distributions are within expected ranges when the supply voltage is low according to the metric of voltage variations. ### Claim 11 (depends on 8) The memory device of claim 8, wherein a bad-block marking error handling procedure is modified to increase error count thresholds used to determine whether a block is bad and marked to prevent future use of the block when the supply voltage is low according to the metric of voltage variations. ### Claim 12 A method for voltage degradation aware memory array management, the memory device comprising: detecting a variation of a supply voltage to a memory array of a memory device, the variation determined to be at least one of a threshold drop in supply voltage from an expected supply voltage or a difference in supply voltage between measurements of the supply voltage; recording the variation of the supply voltage with other detected variations of the supply voltage to create a voltage event history, the voltage event history being a data structure managed by a controller of the memory device; and changing operation of the memory array in response to a metric of voltage variations derived from the voltage event history, the metric of voltage variations measuring a deviation of the supply voltage from a supply voltage for reliable memory array write operations. ### Claim 13 (depends on 12) The method of claim 12, wherein recording the variation of the supply voltage with the other detected variations of the supply voltage includes changing a counter to aggregate the variation of the supply voltage with the other detected variations of the supply voltage. ### Claim 14 (depends on 13) The method of claim 13, wherein the counter is changed in a first direction when the supply voltage is greater than a previous measurement, the counter is changed in a second direction when the supply voltage is less than a previous measurement, and the counter is unchanged otherwise. ### Claim 15 (depends on 13) The method of claim 13, wherein the counter includes a time-based modification such that the counter is an aggregation of only those measurements that are within a time-window to produce a rate of supply voltage variations. ### Claim 16 (depends on 12) The method of claim 12, wherein changing the operation of the memory array includes changing a write procedure to account for a lower voltage to the memory array. ### Claim 17 (depends on 16) The method of claim 16, wherein the write procedure is changed such that data being written is kept in a write buffer after the data is written to the memory array until the data written to the memory array is verified as being correctly written. ### Claim 18 (depends on 17) The method of claim 17, wherein a verification that the data is correctly written includes reading the data from the memory array and comparing a result of the read to the data in the write buffer, the data being correctly written when the result of the read and the data in the write buffer match. ### Claim 19 (depends on 12) The method of claim 12, wherein changing the operation of the memory array includes modifying an error handling procedure of the memory array. ### Claim 20 (depends on 19) The method of claim 19, wherein a read-retry error handling procedure is modified by being initiated earlier to recover read data when the supply voltage is low according to the metric of voltage variations. ### Claim 21 (depends on 19) The method of claim 19, wherein a program-erase error handling procedure is modified to include additional tests to ensure that charge distributions are within expected ranges when the supply voltage is low according to the metric of voltage variations. ### Claim 22 (depends on 19) The method of claim 19, wherein a had-block marking error handling procedure is modified to increase error count thresholds used to determine whether a block is bad and marked to prevent future use of the block when the supply voltage is low according to the metric of voltage variations.