# US 10,311,958 B2 · Array of three-gate flash memory cells with individual memory cell read, program and erase

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- Number: US 10,311,958 B2
- Document ID: US10311958B2
- Status: Granted
- Kind: B2
- Application number: 15/593,231
- Filed: 2017-05-11
- Published: 2017-11-23
- Granted: 2019-06-04
- Earliest claimed: 2016-05-17
- Assignees: Silicon Storage Technology, Inc.
- Applicants: Silicon Storage Technology, Inc.
- Inventors: Hieu Van Tran; Vipin Tiwari; Nhan Do
- Web page: https://patentgrep.com/patent/US10311958B2

## CPC

- G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits
- G11C 16/0425: {comprising cells containing a merged floating gate and select transistor}
- G11C 16/10: Programming or data input circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A memory device and method of erasing same that includes a substrate of semiconductor material and a plurality of memory cells formed on the substrate and arranged in an array of rows and columns. Each of the memory cells includes spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between, a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region, a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and a program-erase gate disposed over and insulated from the source region. The program-erase gate lines alone or in combination with the select gate lines, or the source lines, are arranged in the column direction so that each memory cell can be individually programmed, read and erased.

## Claims

### Claim 1

A memory device, comprising:
a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region,
a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and
a program-erase gate disposed over and insulated from the source region;
each of the columns of memory cells includes a source line that electrically connects together all the source regions for the column of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the rows of memory cells includes a select gate line that electrically connects together all the select gates of the memory cells for the row of memory cells; and
each of the rows of memory cells includes a program-erase gate line that electrically connects together all the program-erase gates of the memory cells for the row of memory cells.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein for each of the memory cells, the floating gate extends over and is insulated from a portion of the source region.

### Claim 3 (depends on 1)

The memory device of claim 1, wherein for each of the memory cells, the select gate has a first portion laterally adjacent to the floating gate and a second portion that extends up and over the floating gate.

### Claim 4 (depends on 1)

The memory device of claim 1, wherein for each of the memory cells, the program-erase gate has a first portion laterally adjacent to the floating gate and a second portion that extends up and over the floating gate.

### Claim 5 (depends on 1)

The memory device of claim 1, wherein:
the memory cells are arranged in pairs of the memory cells; and
each of the pairs of memory cells shares one of the source regions and one of the source lines.

### Claim 6

A memory device, comprising:
a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, wherein the rows of the memory cells are arranged in alternating even and odd numbered rows;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region,
a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and
a program-erase gate disposed over and insulated from the source region;
each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the columns of memory cells includes a first select gate line that electrically connects together all the select gates of the memory cells for the column of memory cells that are in the odd numbered rows or the even numbered rows of the memory cells;
each of the columns of memory cells includes a program-erase gate line that electrically connects together all the program-erase gates of the memory cells for the column of memory cells.

### Claim 7 (depends on 6)

The memory device of claim 6, wherein the first select gate line for each of the columns of memory cells electrically connects together all the select gates of the memory cells for the column of memory cells that are in the odd numbered rows of the memory cells, and wherein each of the columns of memory cells further comprises a second select gate line that electrically connects together all the select gates of the memory cells for the column of memory cells that are in the even numbered rows of the memory cells.

### Claim 8 (depends on 6)

The memory device of claim 6, wherein for each of the memory cells, the floating gate extends over and is insulated from a portion of the source region.

### Claim 9 (depends on 6)

The memory device of claim 6, wherein for each of the memory cells, the select gate has a first portion laterally adjacent to the floating gate and a second portion that extends up and over the floating gate.

### Claim 10 (depends on 6)

The memory device of claim 6, wherein for each of the memory cells, the program-erase gate has a first portion laterally adjacent to the floating gate and a second portion that extends up and over the floating gate.

### Claim 11 (depends on 6)

The memory device of claim 6, wherein:
the memory cells are arranged in pairs of the memory cells; and
each of the pairs of memory cells shares one of the source regions and one of the source lines.

### Claim 12

A method of erasing a selected memory cell of a memory device, wherein the memory device comprises:
a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, and wherein one of the plurality of memory cells is a selected memory cell;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region,
a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and
a program-erase gate disposed over and insulated from the source region;
each of the row of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the rows of memory cells includes a select gate line that electrically connects together all the select gates of the memory cells for the row of memory cells;
each of the columns of memory cells includes a program-erase gate line that electrically connects together all the program-erase gates of the memory cells for the column of memory cells;
the method comprising:
applying a positive voltage to one of the program-erase gate lines that is electrically connected to the program-erase gate of the selected memory cell, and a ground voltage to all the others of the program-erase gate lines;
applying a ground voltage to one of the source lines that is electrically connected to the source region of the selected memory cell, and a positive voltage to all the others of the source lines.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
applying a ground voltage to one of the bit lines that is electrically connected to the drain region of the selected memory cell, and a ground or positive voltage to all the others of the bit lines.

### Claim 14 (depends on 12)

The method of claim 12, wherein the positive voltage applied to the one of the program-erase gate lines is greater than the positive voltage applied to the others of the source lines.

### Claim 15 (depends on 12)

The method of claim 12, wherein the positive voltage applied to the one of the program-erase gate lines is at least double than that of the positive voltage applied to the others of the source lines.

### Claim 16

A method of erasing a selected memory cell of a memory device, wherein the memory device comprises:
a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of rows and columns, and wherein one of the plurality of memory cells is a selected memory cell;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region,
a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and
a program-erase gate disposed over and insulated from the source region;
each of the columns of memory cells includes a source line that electrically connects together all the source regions for the column of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the rows of memory cells includes a select gate line that electrically connects together all the select gates of the memory cells for the row of memory cells;
each of the rows of memory cells includes a program-erase gate line that electrically connects together all the program-erase gates of the memory cells for the row of memory cells;
the method comprising:
applying a positive voltage to one of the program-erase gate lines that is electrically connected to the program-erase gate of the selected memory cell, and a ground voltage to all the others of the program-erase gate lines;
applying a ground voltage to one of the source lines that is electrically connected to the source region of the selected memory cell, and a positive voltage to all the others of the source lines.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
applying a ground voltage to one of the bit lines that is electrically connected to the drain region of the selected memory cell, and a ground or positive voltage to all the others of the bit lines.

### Claim 18 (depends on 16)

The method of claim 16, wherein the positive voltage applied to the one of the program-erase gate lines is greater than the positive voltage applied to the others of the source lines.

### Claim 19 (depends on 16)

The method of claim 16, wherein the positive voltage applied to the one of the program-erase gate lines is at least double than that of the positive voltage applied to the others of the source lines.

### Claim 20

A method of erasing a selected memory cell of a memory device, wherein the memory device comprises:
a substrate of semiconductor material;
a plurality of memory cells formed on the substrate and arranged in an array of even and odd numbered rows and even and odd numbered columns, and wherein one of the plurality of memory cells is a selected memory cell;
each of the memory cells includes:
spaced apart source and drain regions in the substrate, with a channel region in the substrate extending there between,
a floating gate disposed over and insulated from a first portion of the channel region which is adjacent the source region,
a select gate disposed over and insulated from a second portion of the channel region which is adjacent the drain region, and
a program-erase gate disposed over and insulated from the source region;
each of the rows of memory cells includes a source line that electrically connects together all the source regions for the row of memory cells;
each of the columns of memory cells includes a bit line that electrically connects together all the drain regions for the column of memory cells;
each of the columns of memory cells includes a first select gate line that electrically connects together all the select gates of the memory cells for the column of memory cells that are in the odd numbered rows or the even numbered rows of the memory cells;
each of the columns of memory cells includes a program-erase gate line that electrically connects together all the program-erase gates of the memory cells for the column of memory cells;
the method comprising:
applying a positive voltage to one of the program-erase gate lines that is electrically connected to the program-erase gate of the selected memory cell, and a ground voltage to all the others of the program-erase gate lines;
applying a ground voltage to one of the source lines that is electrically connected to the source region of the selected memory cell, and a positive voltage to all the others of the source lines.

### Claim 21 (depends on 20)

The method of claim 20, wherein the first select gate line for each of the columns of memory cells electrically connects together all the select gates of the memory cells for the column of memory cells that are in the odd numbered rows of the memory cells, and wherein each of the columns of memory cells further comprises a second select gate line that electrically connects together all the select gates of the memory cells for the column of memory cells that are in the even numbered rows of the memory cells.

### Claim 22 (depends on 20)

The method of claim 20, further comprising:
applying a ground voltage to one of the bit lines that is electrically connected to the drain region of the selected memory cell, and a ground or positive voltage to all the others of the bit lines.

### Claim 23 (depends on 20)

The method of claim 20, wherein the positive voltage applied to the one of the program-erase gate lines is greater than the positive voltage applied to the others of the source lines.

### Claim 24 (depends on 20)

The method of claim 20, wherein the positive voltage applied to the one of the program-erase gate lines is at least double than that of the positive voltage applied to the others of the source lines.