# US 10,311,956 B2 · Semiconductor memory device and operating method thereof > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,956 B2 - Document ID: US10311956B2 - Status: Granted - Kind: B2 - Application number: 15/884,654 - Filed: 2018-01-31 - Published: 2019-01-10 - Granted: 2019-06-04 - Earliest claimed: 2017-07-10 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Hee Youl Lee - Web page: https://patentgrep.com/patent/US10311956B2 ## CPC - G11C 16/10: Programming or data input circuits - G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection - G11C 11/5628: {Programming or writing circuits; Data input circuits} - G11C 16/30: Power supply circuits - G11C 16/3459: {Circuits or methods to verify correct programming of nonvolatile memory cells} - G11C 11/5642: {Sensing or reading circuits; Data output circuits} - G11C 16/0483: {comprising cells having several storage transistors connected in series} - G11C 16/08: Address circuits; Decoders; Word-line control circuits - G11C 2211/5641: Multilevel memory having cells with different number of storage levels - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Disclosed are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells which are programmed to a plurality of program states, a peripheral circuit configured to perform a program operation on the memory cell array, and a control logic configured to control the peripheral circuit to divide the plurality of program states into two or more program groups and sequentially program the two or more program groups during the program operation, wherein the control logic controls the peripheral circuit to simultaneously program the memory cells which are to be programmed to program states included in the same program group among the plurality of memory cells. ## Claims ### Claim 1 A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells which are programmed to a plurality of program states; a peripheral circuit configured to perform a program operation on the memory cell array; and a control logic configured to control the peripheral circuit to divide the plurality of program states into two or more program groups and sequentially program the two or more program groups during the program operation, wherein the control logic controls the peripheral circuit to simultaneously program the memory cells which are to be programmed to program states included in the same program group among the plurality of memory cells, and wherein the control logic controls the peripheral circuit to first perform a program operation on a first program group having a lower threshold voltage distribution than a second program group among the two or more program groups, and second perform a program operation on the second program group having a higher threshold voltage distribution than the first program group. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein the peripheral circuit includes a read and write circuit connected with bit lines of the memory cell array, and the read and write circuit applies a plurality of program allowable voltages to first bit lines corresponding to a selected program group among the two or more program groups. ### Claim 3 (depends on 2) The semiconductor memory device of claim 2, wherein the read and write circuit applies the plurality of program allowable voltages which correspond to the program states included in the selected program group, respectively, to the first bit lines. ### Claim 4 (depends on 2) The semiconductor memory device of claim 2, wherein the read and write circuit applies a program inhibition voltage to second bit lines corresponding to a remaining unselected program group, not including the selected program group. ### Claim 5 (depends on 4) The semiconductor memory device of claim 4, wherein the plurality of program allowable voltages has a lower potential level than a potential level of the program inhibition voltage. ### Claim 6 (depends on 1) The semiconductor memory device of claim 1, wherein each of the two or more program groups includes adjacent program states among the plurality of program states. ### Claim 7 A semiconductor memory device, comprising: a memory cell array including a plurality of memory cells which are programmed to a plurality of program states; a peripheral circuit configured to perform a program operation on the memory cell array; and a control logic configured to control the peripheral circuit to group the plurality of program states into a first program group and a second program group, and perform a program operation on the first program group and then perform a program operation on the second program group during the program operation, wherein the control logic groups program states, which have low threshold voltage distributions and are adjacent to one another, among the plurality of program states into the first program group, and groups program states, which have relatively higher threshold voltage distributions than the low threshold voltage distributions and are adjacent to one another, among the plurality of program states into the second program group. ### Claim 8 (depends on 7) The semiconductor memory device of claim 7, wherein the control logic simultaneously programs first memory cells to be programmed to the program states included in the first program group among the plurality of memory cells, and simultaneously programs second memory cells to be programmed to the program states included in the second program group among the plurality of memory cells. ### Claim 9 (depends on 8) The semiconductor memory device of claim 8, wherein the peripheral circuit includes a read and write circuit connected with bit lines of the memory cell array, and the read and write circuit applies a plurality of program allowable voltages to first bit lines corresponding to a selected program group between the first program group and the second program group. ### Claim 10 (depends on 9) The semiconductor memory device of claim 9, wherein the read and write circuit applies the plurality of program allowable voltages which correspond to the program states included in the selected program group, respectively, to the first bit lines. ### Claim 11 (depends on 9) The semiconductor memory device of claim 9, wherein the read and write circuit applies a program inhibition voltage to second bit lines corresponding to an unselected program group between the first program group and the second program group. ### Claim 12 (depends on 11) The semiconductor memory device of claim 11, wherein the plurality of program allowable voltages has a lower potential level than a potential level of the program inhibition voltage. ### Claim 13 (depends on 9) The semiconductor memory device of claim 9, wherein when a first program state to be programmed has a higher threshold voltage than a second program state, the read and write circuit applies a lower program allowable voltage among the plurality of program allowable voltages to a bit line corresponding to the first program state than applied to a bit line corresponding to the second program state, and when the first program state to be programmed has a lower threshold voltage than the second program state, the read and write circuit applies a higher program allowable voltage among the plurality of program allowable voltages to the bit line corresponding to the first program state than applied to the bit line corresponding to the second program state. ### Claim 14 A method of operating a semiconductor memory device, the method comprising: receiving a plurality of data to be programmed from the outside the semiconductor device, and storing the received data in a read and write circuit connected with bit lines of a memory cell array; grouping the plurality of data into a plurality of program groups; performing a program operation on a selected program group among the plurality of program groups; and when a program operation for the selected program group is completed, performing a program operation on a next program group, wherein the grouping of the plurality of data into the plurality of program groups includes grouping the plurality of data into the plurality of program groups according to a plurality of program states corresponding to the plurality of data and grouping the program states having threshold voltage distributions adjacent to one another into one program group. ### Claim 15 (depends on 14) The method of claim 14, wherein a program inhibition voltage is applied to second bit lines corresponding to a unselected program group among the bit lines during the program operation for the selected program group.