# US 10,311,955 B2 · Resistive memory transition monitoring > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,955 B2 - Document ID: US10311955B2 - Status: Granted - Kind: B2 - Application number: 16/058,552 - Filed: 2018-08-08 - Published: 2018-12-06 - Granted: 2019-06-04 - Earliest claimed: 2016-03-02 - Assignees: Infineon Technologies AG - Applicants: Infineon Technologies AG - Inventors: Ulrich Backhausen; Giacomo Curatolo; Jens Rosenbusch - Web page: https://patentgrep.com/patent/US10311955B2 ## CPC - G11C 13/0097: {Erasing, e.g. resetting, circuits or methods} - G01R 31/1227: {of components, parts or materials (G01R31/1209, G01R31/1218, G01R31/18 take precedence; circuits therefor G01R31/14; testing vessels of electrodes G01R31/16)} - G01R 31/14: Circuits therefor {, e.g. for generating test voltages, sensing circuits (G01R31/1209 - G01R31/1227 take precedence; for testing switches G01R31/327)} - G01R 31/2856: {Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0061: {Timing circuits or methods} - G11C 13/0064: {Verifying circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 29/021: {in voltage or current generators} - G11C 29/028: {with adaption or trimming of parameters} - G11C 13/0026: {Bit-line or column circuits} - G11C 13/0028: {Word-line or row circuits} - G11C 2013/0045: {Read using current through the cell} - G11C 2013/0054: {Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell} - G11C 2013/0066: {Verify correct writing whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cell and using the detector output to terminate writing} - G11C 2013/0083: {Write to perform initialising, forming process, electro forming or conditioning} - G11C 2029/5006: {Current} - G11C 2213/79: Array wherein the access device being a transistor - G11C: STATIC STORES (semiconductor memory devices H10B) - G01R: MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES (indicating correct tuning of resonant circuits H03J3/12) ## Abstract A method for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines. The method includes determining, by a current determining circuit, a cell current and a cell current change rate of at least one of the cells; determining, by a control circuit, whether the cell current change rate is outside of a cell current change rate predefined range; performing, by the control circuit, a predetermined action if the control circuit determination is positive; and storing, in a memory, the determined cell current at predetermined times, and to store the determined cell current change rate. ## Claims ### Claim 1 A method for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines, the method comprising: determining, by a current determining circuit, a cell current and a cell current change rate of at least one of the cells; determining, by a control circuit, whether the cell current change rate is outside of a cell current change rate predefined range; performing, by the control circuit, a predetermined action if the control circuit determination is positive; and storing, in a memory, the determined cell current at predetermined times, and to store the determined cell current change rate. ### Claim 2 (depends on 1) The method of claim 1, wherein the predetermined action is a dynamic adjustment of a bitline voltage and/or a wordline voltage of the at least one cell, performed during a cell resistance transition sequence of the at least one cell. ### Claim 3 (depends on 1) The method of claim 1, further comprising: determining, by the current determining circuit, a cell current and a cell current change rate of a plurality of the cells; determining, by the control circuit, whether the cell current change rate of any of the plurality of cells is outside of the cell current change rate predefined range; and performing, by the control circuit, the predetermined action if the control circuit determination is positive for any of the cells. ### Claim 4 (depends on 3) The method of claim 3, wherein each of the plurality of cells has an individual cell current change rate predefined range. ### Claim 5 (depends on 3) The method of claim 3, further comprising: determining, by the current determining circuit, the cell current and the cell current change rate of the plurality of cells sequentially. ### Claim 6 (depends on 1) The method of claim 1, further comprising: determining, by the current determining circuit, the cell current and the cell current change rate of a plurality of cells simultaneously; determining, by the control circuit, whether a median of the cell current change rate of the plurality of cells is outside of a median cell current change rate predefined range; and performing, by the control circuit, a predetermined action if the control circuit determination is positive. ### Claim 7 (depends on 1) The method of claim 1, wherein the predetermined action is stopping a cell resistance transition sequence of the at least one cell. ### Claim 8 (depends on 1) The method of claim 1, wherein the cell current change rate predefined range is based on a compliance setting of the cell current or of the cell current change rate. ### Claim 9 (depends on 1) The method of claim 1, further comprising: ramping, by the control circuit, a wordline voltage and/or a bitline voltage of the at least one cell until a predetermined cell current change rate is reached. ### Claim 10 (depends on 1) The method of claim 1, wherein the predetermined action is replacing the at least one cell with a redundant cell. ### Claim 11 (depends on 1) The method of claim 1, further comprising: determining, by the current determining circuit, the cell current and the cell current change rate during a cell resistance transition sequence of the at least one cell. ### Claim 12 (depends on 11) The method of claim 11, wherein the cell resistance transition sequence is a set operation, a reset operation, and/or a forming operation of the at least one cell. ### Claim 13 (depends on 1) The method of claim 1, wherein the determining, by the current determining circuit, the cell current and the cell current change rate of at least one of the cells, comprises: generating, by a reference voltage generation circuit, a sweep of reference voltages at periodic times; and comparing, by a comparator, a shunt voltage, which is between the at least one cell and ground, with the sweep of reference voltages at the periodic times until the shunt voltage crosses the sweep of reference voltages to determine the shunt voltage. ### Claim 14 (depends on 13) The method of claim 13, further comprising: determining, by a differentiator, the shunt voltage change rate; and determining, by the control circuit, the cell current and the cell current change rate based on the shunt voltage and the shunt voltage change rate. ### Claim 15 (depends on 13) The method of claim 13, further comprising: storing, by the memory, the shunt voltages and the corresponding periodic times; and determining, by the control circuit, the cell current change rate based on the stored shunt voltages and the corresponding periodic times. ### Claim 16 (depends on 13) The method of claim 13, further comprising: determining the sweep of reference voltages dynamically determined based on an initial shunt voltage. ### Claim 17 (depends on 1) The method of claim 1, wherein the determining, by the current determining circuit, the cell current and the cell current change rate of at least one of the cells, comprises: comparing, by a plurality of comparators, a shunt voltage, which is between the at least one cell and ground, with respective reference voltages to determine the shunt voltage; determining, by a differentiator, the shunt voltage change rate; and determining, by the control circuit, the cell current and the cell current change rate based on the shunt voltage and the shunt voltage change rate. ### Claim 18 A method for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines, the method comprising: determining, by a current determining circuit, a cell current and a cell current change rate of at least one of the cells; determining, by a control circuit, whether the cell current change rate is outside of a cell current change rate predefined range; and performing, by the control circuit, a predetermined action if the control circuit determination is positive, wherein the predetermined action is a static adjustment of a bitline voltage and/or a wordline voltage of the at least one cell, performed between cell resistance transition sequences. ### Claim 19 A method for monitoring a resistive memory having an array of cells coupled between respective bitlines and respective wordlines, the method comprising: determining, by a current determining circuit, a cell current and a cell current change rate of at least one of the cells; determining, by a control circuit, whether the cell current change rate is outside of a cell current change rate predefined range; and performing, by the control circuit, a predetermined action if the control circuit determination is positive, wherein the predetermined action is replacing the at least one cell with a redundant cell.