# US 10,311,954 B2 · Memory cell architecture for multilevel cell programming

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- Number: US 10,311,954 B2
- Document ID: US10311954B2
- Status: Granted
- Kind: B2
- Application number: 16/045,526
- Filed: 2018-07-25
- Published: 2018-12-13
- Granted: 2019-06-04
- Earliest claimed: 2016-02-17
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Mario Allegra; Mattia Boniardi
- Web page: https://patentgrep.com/patent/US10311954B2

## CPC

- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 11/5628: {Programming or writing circuits; Data input circuits}
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- H10B 63/20: {comprising selection components having two electrodes, e.g. diodes}
- H10B 63/24: {of the Ovonic threshold switching type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/882: {Compounds of sulfur, selenium or tellurium, e.g. chalcogenides}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- G11C 2013/009: {Write using potential difference applied between cell electrodes}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Methods, systems, and devices for operating and forming a multilevel memory cell and array are described. A multilevel memory cell includes two or more binary memory elements, which may include phase change material. Each memory element may be programmed to one of two possible states—e.g., a fully amorphous state or a fully crystalline state. By combining multiple binary memory elements in a single memory cell, the memory cell may be programmed to store more than two states. The different memory elements may be programmed by selectively melting each memory element. Selective melting may be controlled by using memory elements with different melting temperatures or using electrodes with different electrical resistances, or both.

## Claims

### Claim 1

An apparatus, comprising:
a memory cell comprising a first memory element positioned between a first electrode and a second electrode and a second memory element positioned between the second electrode and a third electrode; and
a memory controller coupled with the first memory element and the second memory element, the memory controller operable to:
apply a first current to the first memory element and the second memory element, wherein a logic value stored by the first memory element is based at least in part on a magnitude of the first current; and
apply a second current to the first memory element and the second memory element, wherein a magnitude of the second current is based at least in part on a melting temperature of the first memory element or the second memory element.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein at least a portion of the first memory element and at least a portion of the second memory element are each configured to one of an amorphous state or a crystalline state based at least in part on applying the first current and applying the second current.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein the memory controller is configured to:
determine a logic state of the memory cell, wherein the logic state of the memory cell is based at least in part on the first memory element comprising the amorphous state or the crystalline state, and the second memory element comprising the amorphous state or the crystalline state.

### Claim 4 (depends on 1)

The apparatus of claim 1, further comprising:
a bit line coupled with the first electrode, wherein the first electrode is coupled with the first memory element;
a word line coupled with the third electrode, wherein the third electrode is coupled with the second memory element, wherein the memory controller is configured to:
apply a voltage to the memory cell, wherein the first current or the second current is based at least in part on applying the voltage to the memory cell.