# US 10,311,952 B2 · Method and apparatus for reading RRAM cell

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- Number: US 10,311,952 B2
- Document ID: US10311952B2
- Status: Granted
- Kind: B2
- Application number: 15/937,257
- Filed: 2018-03-27
- Published: 2018-08-02
- Granted: 2019-06-04
- Earliest claimed: 2016-02-16
- Assignees: Taiwan Semiconductor Manufacturing Company, Ltd.
- Applicants: Taiwan Semiconductor Manufacturing Co., Ltd.
- Inventors: Chin-Chieh Yang; Chih-Yang Chang; Chang-Sheng Liao; Hsia-Wei Chen; Jen-Sheng Yang; Kuo-Chi Tu; Sheng-Hung Shih; Wen-Ting Chu; Manish Kumar Singh; Chi-Tsai Chen
- Web page: https://patentgrep.com/patent/US10311952B2

## CPC

- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 11/1653: {Address circuits or decoders}
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 13/0023: {Address circuits or decoders}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 2213/79: Array wherein the access device being a transistor
- G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

In some embodiments, the present disclosure relates to a resistive random access memory (RRAM) memory circuit. The memory circuit has a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line. A bit-line decoder is coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line. A bias element is configured to apply a first non-zero bias voltage to the second bit-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line.

## Claims

### Claim 1

A resistive random access memory (RRAM) memory circuit, comprising:
a word-line decoder operably coupled to a first RRAM device and a second RRAM device by a word-line;
a bit-line decoder coupled to the first RRAM device by a first bit-line and to the second RRAM device by a second bit-line;
a source-line decoder coupled to the first RRAM device by a first source-line and to the second RRAM device by a second source-line; and
a bias element configured to concurrently apply a first non-zero bias voltage to the second bit-line and to the second source-line concurrent to the bit-line decoder applying a non-zero voltage to the first bit-line during a read operation.

### Claim 2 (depends on 1)

The memory circuit of claim 1,
a control unit configured to output a first address to the bit-line decoder and a second address to the bias element; and
wherein the bit-line decoder is configured to selectively apply the non-zero voltage to the first bit-line based upon the first address and the bias element is configured to selectively apply the first non-zero bias voltage to the second bit-line based upon the second address.

### Claim 3 (depends on 1)

The memory circuit of claim 1, further comprising:
a first access transistor having a first gate terminal coupled to the word-line, a first drain terminal coupled to the first RRAM device, and a first source terminal; and
a second access transistor having a second gate terminal coupled to the word-line, a second drain terminal coupled to the second RRAM device, and a second source terminal.

### Claim 4 (depends on 3)

The memory circuit of claim 3, wherein the first source-line is coupled to the first source terminal and the second source-line is coupled to the second source terminal.

### Claim 5 (depends on 4)

The memory circuit of claim 4, wherein the read operation is performed to read a data state from the first RRAM device.

### Claim 6 (depends on 4)

The memory circuit of claim 4, wherein the bias element is configured to apply the first non-zero bias voltage to the second bit-line concurrent to the word-line decoder applying a non-zero word-line voltage to the word-line.

### Claim 7

A memory circuit, comprising:
a memory array;
a word-line decoder configured to apply a first non-zero read voltage to a word-line coupled to a selected memory cell and to a plurality of unselected memory cells within the memory array;
a bit-line decoder configured to apply a second non-zero read voltage to a first bit-line coupled to the selected memory cell during a read operation; and
a bias element configured to apply a first non-zero bias voltage to additional bit-lines coupled to the plurality of unselected memory cells concurrent to the bit-line decoder applying the second non-zero read voltage to the first bit-line during the read operation.

### Claim 8 (depends on 7)

The memory circuit of claim 7, wherein the bias element is configured to apply the first non-zero bias voltage to the additional bit-lines concurrent to the word-line decoder applying the first non-zero read voltage to the word-line.

### Claim 9 (depends on 7)

The memory circuit of claim 7, wherein the selected memory cell and the plurality of unselected memory cells are RRAM cells.

### Claim 10 (depends on 9)

The memory circuit of claim 9, further comprising:
an access transistor having a gate terminal coupled to the word-line, a drain terminal coupled to one of the plurality of unselected memory cells, and a source terminal coupled to a source-line; and
wherein the bias element is configured to apply a second non-zero bias voltage to the source-line concurrent to the bit-line decoder applying the second non-zero read voltage to the first bit-line.

### Claim 11 (depends on 10)

The memory circuit of claim 10, further comprising:
a second access transistor having a second gate terminal coupled to the word-line, a second drain terminal coupled to the selected memory cell, and a second source terminal coupled to a second source-line; and
wherein the bias element is configured to not apply a non-zero bias voltage to the second source-line concurrent to the bit-line decoder applying the second non-zero read voltage to the first bit-line.

### Claim 12

A method of operating a resistive random access memory (RRAM) array, comprising:
performing a read operation on a selected RRAM device, by:
activating a word-line coupled to the selected RRAM device and a plurality of unselected RRAM devices by applying a word-line voltage to the word-line;
applying a first non-zero bit-line voltage to a first bit-line coupled to the selected RRAM device; and
applying a first non-zero bias voltage to a plurality of additional bit-lines or applying a second non-zero bias voltage to a plurality of additional select-lines concurrent to applying the first non-zero bit-line voltage to the first bit-line, wherein the plurality of additional bit-lines and the plurality of additional select-lines are coupled to the plurality of unselected RRAM devices.

### Claim 13 (depends on 12)

The method of claim 12, further comprising:
concurrently applying the first non-zero bias voltage to the plurality of additional bit-lines, the second non-zero bias voltage to the plurality of additional select-lines, and the first non-zero bit-line voltage to the first bit-line.

### Claim 14 (depends on 12)

The method of claim 12, wherein a difference between the word-line voltage and the first non-zero bias voltage or the second non-zero bias voltage is approximately equal to 1.1 volts.

### Claim 15 (depends on 12)

The method of claim 12, wherein the first non-zero bias voltage is substantially equal to the second non-zero bias voltage.

### Claim 16 (depends on 12)

The method of claim 12, wherein the first non-zero bit-line voltage, the first non-zero bias voltage, and the second non-zero bias voltage are substantially equal.

### Claim 17 (depends on 12)

The method of claim 12, further comprising:
performing a set operation on the selected RRAM device, wherein performing the set operation comprises concurrently applying a first set voltage to the word-line and a second set voltage to the first bit-line.

### Claim 18 (depends on 17)

The method of claim 17, wherein a difference between the first non-zero bit-line voltage and the first non-zero bias voltage is approximately equal to the first set voltage.

### Claim 19 (depends on 17)

The method of claim 17, wherein the word-line voltage is larger than the first set voltage.

### Claim 20 (depends on 12)

The method of claim 12, wherein the word-line voltage and the first non-zero bit-line voltage are used to read a stored data state from the selected RRAM device.