# US 10,311,951 B2 · Refresh architecture and algorithm for non-volatile memories

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- Number: US 10,311,951 B2
- Document ID: US10311951B2
- Status: Granted
- Kind: B2
- Application number: 16/108,828
- Filed: 2018-08-22
- Published: 2018-12-20
- Granted: 2019-06-04
- Earliest claimed: 2015-06-29
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Ferdinando Bedeschi; Roberto Gastaldi
- Web page: https://patentgrep.com/patent/US10311951B2

## CPC

- G11C 13/0033: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G06F 11/1068: {in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence)}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0038: {Power supply circuits}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0061: {Timing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 14/009: {and the nonvolatile element is a resistive RAM element, i.e. programmable resistors, e.g. formed of phase change or chalcogenide material}
- G11C 16/3418: {Disturbance prevention or evaluation; Refreshing of disturbed memory data}
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 11/5678: {using amorphous/crystalline phase transition storage elements}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

Methods and systems to refresh a nonvolatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of error-corrected memory cells using a non-margined read reference level.

## Claims

### Claim 1

A method of refreshing a memory array in a non-volatile memory device, the method comprising:
entering a system-on state;
entering an active state after entering the system-on state;
entering a standby state after the entering the active state;
entering a system-off state after entering the standby state; and
performing a refresh operation in the non-volatile memory device after entering the system-off state, wherein the non-volatile memory device is powered by a same power unit before and after the refresh operation is performed.

### Claim 2 (depends on 1)

The method of claim 1, wherein:
performing the refresh operation includes reading every operational cell in the memory array.

### Claim 3 (depends on 1)

The method of claim 1, wherein performing the refresh operation includes:
reading cells of the memory array against a reference level; and
reprogramming cells that fail the reference level.

### Claim 4 (depends on 1)

The method of claim 1, wherein the refresh operation is performed repetitively at a frequency based on a temperature of the non-volatile memory device after entering the system-off state.

### Claim 5 (depends on 1)

The method of claim 1, wherein the refresh operation is performed in response to an increase in temperature when non-volatile memory device enters the system-off state.

### Claim 6 (depends on 1)

The method of claim 1, wherein the non-volatile memory device receives power from an automobile battery.

### Claim 7 (depends on 6)

The method of claim 6, wherein the non-volatile memory device enters the system-on state when an automobile ignition is actuated.

### Claim 8 (depends on 1)

The method of claim 1, wherein the non-volatile memory device receives power from an automobile battery, and entering the system-off state occurs when an automobile ignition is actuated.

### Claim 9 (depends on 1)

The method of claim 1, wherein the non-volatile memory device receives power from an automobile battery, and wherein:
entering the system-on state occurs when an automobile ignition is actuated to turn an engine on; and
entering the system-off state occurs when the automobile ignition is actuated to turn the engine off.

### Claim 10

A non-volatile memory device comprising:
a memory array; and
a refresh controller coupled to the memory array, the refresh controller configured to control a refresh operation performed on the memory array after a system-off state is entered, wherein the system-off occurs after the non-volatile memory device enters a system-on state, an active state after entering the system-on state, and a standby state after the entering the active state, wherein the non-volatile memory device is powered by a same power unit before and after the refresh operation is performed.

### Claim 11 (depends on 10)

The non-volatile memory device of claim 10, wherein the refresh controller is configured to initiate the refresh operation in response to output from a temperature sensor.

### Claim 12 (depends on 10)

The non-volatile memory device of claim 10, wherein the refresh controller is configured to initiate the refresh operation in response to output from a refresh timer.

### Claim 13 (depends on 10)

The non-volatile memory device of claim 10, wherein the non-volatile memory device is configured to receive power from an automobile battery, and the refresh controller is configured to initiate the refresh operation when an automobile ignition is actuated.

### Claim 14 (depends on 10)

The non-volatile memory device of claim 10, wherein the refresh controller is configured to control reprogramming of cells in the subset of the memory array, such that the cells store data corrected by an error correction encoding algorithm.

### Claim 15 (depends on 14)

The non-volatile memory device of claim 14, wherein the refresh controller is configured to control:
reading of cells of the memory array against a reference level during the refresh operation; and
reprogramming of cells that fail the reference level during the refresh operation.

### Claim 16

A system comprising:
a power supply unit configured to couple to an automobile battery;
a memory controller unit coupled to the power supply unit; and
a non-volatile memory device coupled to the memory controller unit, the non-volatile memory device including a memory array, the non-volatile memory device configured to:
enter a system-on state;
enter an active state after entering the system-on state;
enter standby state after the entering the active state;
enter a system-off state after entering the standby state; and
perform a refresh operation in the non-volatile memory device after entering the system-off state, wherein the non-volatile memory device is powered by a same power unit before and after the refresh operation is performed.

### Claim 17 (depends on 16)

The system of claim 16, wherein the non-volatile memory device is configured to read every operational cell in the memory array during the refresh operation.

### Claim 18 (depends on 16)

The system of claim 16, wherein the non-volatile memory device is configured to reprogram cells in the subset of the memory array, such that the cells store data corrected by an error correction encoding algorithm.

### Claim 19 (depends on 18)

The system of claim 18, wherein the non-volatile memory device is configured to:
read cells of the memory array against a reference level during the refresh operation; and
reprogram cells that fail the reference level.

### Claim 20 (depends on 16)

The system of claim 16, wherein the non-volatile memory device is configured to perform the refresh operation in response to an increase in temperature when automobile ignition is actuated to turn an engine off.