# US 10,311,950 B2 · Conductive metal oxide structures in non-volatile re-writable memory devices

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- Number: US 10,311,950 B2
- Document ID: US10311950B2
- Status: Granted
- Kind: B2
- Application number: 15/706,356
- Filed: 2017-09-15
- Published: 2018-04-26
- Granted: 2019-06-04
- Earliest claimed: 2008-12-19
- Assignees: Unity Semiconductor Corporation
- Applicants: Unity Semiconductor Corporation
- Inventors: Lawrence Schloss; Julie Casperson Brewer; Wayne Kinney; Rene Meyer
- Web page: https://patentgrep.com/patent/US10311950B2

## CPC

- G11C 13/0026: {Bit-line or column circuits}
- G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0002: {using resistive RAM [RRAM] elements}
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites}
- G11C 13/0028: {Word-line or row circuits}
- G11C 13/003: {Cell access}
- G11C 13/004: {Reading or sensing circuits or methods}
- H10B 63/10: Phase change RAM [PCRAM, PRAM] devices
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}
- H10N 70/24: {based on migration or redistribution of ionic species, e.g. anions, vacancies}
- H10N 70/245: {the species being metal cations, e.g. programmable metallization cells}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- H10N 70/883: {Oxides or nitrides}
- H10N 70/8833: {Binary metal oxides, e.g. TaOx}
- H10N 70/8836: {Complex metal oxides, e.g. perovskites, spinels}
- G11C 2013/0045: {Read using current through the cell}
- G11C 2013/0073: {Write using bi-directional cell biasing}
- G11C 2213/31: Material having complex metal oxide, e.g. perovskite structure
- G11C 2213/32: Material having simple binary metal oxide structure
- G11C 2213/56: Structure including two electrodes, a memory active layer and a so called passive or source or reservoir layer which is NOT an electrode, wherein the passive or source or reservoir layer is a source of ions which migrate afterwards in the memory active layer to be only trapped there, to form conductive filaments there or to react with the material of the memory active layer in redox way
- G11C 2213/71: Three dimensional array
- G11C 2213/72: Array wherein the access device being a diode
- G11C 2213/74: Array wherein each memory cell has more than one access device
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

A memory cell including a memory element comprising an electrolytic insulator in contact with a conductive metal oxide (CMO) is disclosed. The CMO includes a crystalline structure and can comprise a pyrochlore oxide, a conductive binary oxide, a multiple B-site perovskite, and a Ruddlesden-Popper structure. The CMO includes mobile ions that can be transported to/from the electrolytic insulator in response to an electric field of appropriate magnitude and direction generated by a write voltage applied across the electrolytic insulator and CMO. The memory cell can include a non-ohmic device (NOD) that is electrically in series with the memory element. The memory cell can be positioned between a cross-point of conductive array lines in a two-terminal cross-point memory array in a single layer of memory or multiple vertically stacked layers of memory that are fabricated over a substrate that includes active circuitry for data operations on the array layer(s).

## Claims

### Claim 1

An integrated circuit comprising:
a cross-point memory array comprising a plurality of row conductors and a plurality of column conductors arranged substantially orthogonal to the plurality of row conductors, where each intersection between one of the plurality of row conductors and one of the plurality of column conductors forms a memory cell;
an address unit coupled to at least a portion of the row conductors and to at least a portion of the column conductors in the cross-point memory array, the address unit to receive an address, decode the address, and select a first memory cell corresponding to the address from the cross-point memory array; and
a sense unit coupled to at least the portion of the row conductors and to at least the portion of the column conductors in the cross-point memory array, the sense unit to sense one or more currents flowing through at least one of the row conductors or the column conductors, the one or more currents indicative of stored data in the first memory cell.

### Claim 2 (depends on 1)

The integrated circuit of claim 1, further comprising:
a first plurality of conductive column traces to couple the address unit and the sense unit to the cross-point memory array; and
a second plurality of conductive row traces to couple the address unit and the sense unit to the cross-point memory array.

### Claim 3 (depends on 2)

The integrated circuit of claim 2, wherein to select the first memory cell corresponding to the address, the address unit to apply a select voltage potential to at least one of the first plurality of conductive column traces and at least one of the second plurality of conductive row traces corresponding to the first memory cell.

### Claim 4 (depends on 3)

The integrated circuit of claim 3, wherein the address unit further to apply a non-select voltage potential to unselected traces of the first plurality of conductive column traces and the second plurality of conductive row traces.

### Claim 5 (depends on 1)

The integrated circuit of claim 1, wherein the cross-point memory array comprises:
a base layer; and
one or more memory layers formed above the base layer.

### Claim 6 (depends on 5)

The integrated circuit of claim 5, wherein each of the one or more memory layers is electrically isolated from adjacent layers by a dielectric material.

### Claim 7 (depends on 5)

The integrated circuit of claim 5, wherein memory cells in adjacent layers share at least one of the plurality of row conductors or the plurality of column conductors.

### Claim 8 (depends on 5)

The integrated circuit of claim 5, wherein the base layer comprises a bulk silicon semiconductor substrate upon which a plurality of active memory access circuits are formed, the active memory access circuits to perform data operations on the one or more memory layers.

### Claim 9 (depends on 8)

The integrated circuit of claim 8, wherein the active memory access circuits to apply a select voltage potential to selected row conductors and column conductors of the cross-point memory array through vias coupling the base layer and the one or more memory layers and to apply an unselect voltage potential to unselected row conductors and column conductors of the cross-point memory array.

### Claim 10

A memory device comprising:
a first memory layer comprising a plurality of row conductors and a plurality of column conductors arranged substantially orthogonal to the plurality of row conductors, where each intersection between one of the plurality of row conductors and one of the plurality of column conductors forms a memory cell;
an address unit coupled to at least a portion of the row conductors and to at least a portion of the column conductors in the first memory layer, the address unit to receive an address, decode the address, and select a first memory cell corresponding to the address from the cross-point memory array; and
a sense unit coupled to at least the portion of the row conductors and to at least the portion of the column conductors in the first memory layer, the sense unit to sense one or more currents flowing through at least one of the row conductors or the column conductors, the one or more currents indicative of stored data in the first memory cell.

### Claim 11 (depends on 10)

The memory device of claim 10, further comprising:
a first plurality of conductive column traces to couple the address unit and the sense unit to the first memory layer; and
a second plurality of conductive row traces to couple the address unit and the sense unit to the first memory layer.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein to select the first memory cell corresponding to the address, the address unit to apply a select voltage potential to at least one of the first plurality of conductive column traces and at least one of the second plurality of conductive row traces corresponding to the first memory cell.

### Claim 13 (depends on 12)

The memory device of claim 12, wherein the address unit further to apply a non-select voltage potential to unselected traces of the first plurality of conductive column traces and the second plurality of conductive row traces.

### Claim 14 (depends on 10)

The memory device of claim 10, wherein the first memory layer comprises a cross-point memory array.

### Claim 15 (depends on 10)

The memory device of claim 10, further comprising:
one or more additional memory layers adjacent to the first memory layer, wherein each of the one or more additional memory layers comprises a cross-point memory array.

### Claim 16

A system comprising:
a processing device; and
a memory device coupled to the processing device, the memory device comprising:
a cross-point memory array comprising a plurality of row conductors and a plurality of column conductors arranged substantially orthogonal to the plurality of row conductors, where each intersection between one of the plurality of row conductors and one of the plurality of column conductors forms a memory cell;
an address unit coupled to at least a portion of the row conductors and to at least a portion of the column conductors in the cross-point memory array, the address unit to receive an address, decode the address, and select a first memory cell corresponding to the address from the cross-point memory array; and
a sense unit coupled to at least the portion of the row conductors and to at least the portion of the column conductors in the cross-point memory array, the sense unit to sense one or more currents flowing through at least one of the row conductors or the column conductors, the one or more currents indicative of stored data in the first memory cell.

### Claim 17 (depends on 16)

The system of claim 16, further comprising:
a first plurality of conductive column traces to couple the address unit and the sense unit to the cross-point memory array; and
a second plurality of conductive row traces to couple the address unit and the sense unit to the cross-point memory array.

### Claim 18 (depends on 17)

The system of claim 17, wherein to select the first memory cell corresponding to the address, the address unit to apply a select voltage potential to at least one of the first plurality of conductive column traces and at least one of the second plurality of conductive row traces corresponding to the first memory cell.

### Claim 19 (depends on 18)

The system of claim 18, wherein the address unit further to apply a non-select voltage potential to unselected traces of the first plurality of conductive column traces and the second plurality of conductive row traces.

### Claim 20 (depends on 16)

The system of claim 16, further comprising:
a control unit coupled to the address unit and to the sense unit, the control unit to coordinate operation of the address unit and the sense unit during memory access operations.