# US 10,311,949 B2 · Memory and electronic devices with reduced operational energy in chalcogenide material

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- Number: US 10,311,949 B2
- Document ID: US10311949B2
- Status: Granted
- Kind: B2
- Application number: 15/864,995
- Filed: 2018-01-08
- Published: 2018-05-24
- Granted: 2019-06-04
- Earliest claimed: 2009-06-08
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Roy E. Meade
- Web page: https://patentgrep.com/patent/US10311949B2

## CPC

- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0069: {Writing or programming circuits or methods}
- G11C 13/0097: {Erasing, e.g. resetting, circuits or methods}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/801: {Constructional details of multistable switching devices}
- H10N 70/8413: {adapted for resistive heating}
- H10N 70/8828: {Tellurides, e.g. GeSbTe}
- G11C 7/04: with means for avoiding disturbances due to temperature effects
- G11C 2013/0095: {Write using strain induced by, e.g. piezoelectric, thermal effects}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.

## Claims

### Claim 1

A memory device, comprising:
a chalcogenide material between a first electrode and a second electrode; and
a stress material surrounding a sidewall of the chalcogenide material, the stress material configured to apply a lateral stress upon the chalcogenide material in response to a temperature change or an electrical field,
the first electrode defining a lesser lateral width than a lateral width defined by the chalcogenide material.

### Claim 2 (depends on 1)

The memory device of claim 1, wherein the stress material has a coefficient of thermal expansion differing from a coefficient of thermal expansion exhibited by the chalcogenide material.

### Claim 3 (depends on 2)

The memory device of claim 2, wherein the stress material is directly laterally adjacent the chalcogenide material.

### Claim 4 (depends on 2)

The memory device of claim 2, wherein an upper surface of the stress material is coplanar with an upper surface of the chalcogenide material.

### Claim 5 (depends on 4)

The memory device of claim 4, wherein the stress material extends laterally adjacent at least a portion of the first electrode.

### Claim 6 (depends on 4)

The memory device of claim 4, wherein a lower surface of the stress material is coplanar with a lower surface of the chalcogenide material.

### Claim 7 (depends on 1)

The memory device of claim 1, wherein the stress material is a piezoelectric material.

### Claim 8 (depends on 7)

The memory device of claim 7, further comprising additional electrodes configured to apply the electrical field, the piezoelectric material being disposed between the additional electrodes.

### Claim 9 (depends on 7)

The memory device of claim 7, further comprising a dielectric material between the chalcogenide material and the piezoelectric material.

### Claim 10 (depends on 1)

The memory device of claim 1, wherein the chalcogenide material is selected from the group consisting of GeSbTe (GST), GeTe, AgInSbTe, InSe, SbSe, SbTe, InSbSe, InSbTe, GeSbSe, and GeSbTeSe.

### Claim 11

A memory device, comprising:
a memory cell comprising:
a first electrode;
a second electrode; and
a chalcogenide material disposed between the first electrode and the second electrode, the chalcogenide material having a first coefficient of thermal expansion; and
a thermal expansion material at least partially surrounding the chalcogenide material of the memory cell, the thermal expansion material having a second coefficient of thermal expansion differing from the first coefficient of thermal expansion of the chalcogenide material, the thermal expansion material selected to stress the chalcogenide material upon heating or cooling of the thermal expansion material during operation of the memory device.

### Claim 12 (depends on 11)

The memory device of claim 11, wherein the chalcogenide material is wider than the first electrode.

### Claim 13 (depends on 11)

The memory device of claim 11, wherein the thermal expansion material extends entirely circumferentially around the chalcogenide material.

### Claim 14 (depends on 11)

The memory device of claim 11, wherein the second coefficient of thermal expansion is at least 1.5 times the first coefficient of thermal expansion.

### Claim 15 (depends on 11)

The memory device of claim 11, wherein the thermal expansion material comprises benzocyclobutene.

### Claim 16 (depends on 11)

The memory device of claim 11, wherein at least a portion of the thermal expansion material extends under a lower surface of the chalcogenide material.

### Claim 17

An electronic device, comprising:
an array of memory devices, at least one memory device of the array comprising:
an upper electrode;
a lower electrode;
a chalcogenide material between the upper electrode and the lower electrode, the chalcogenide material extending laterally beyond a sidewall of the lower electrode; and
a stress material laterally adjacent the chalcogenide material and configured to apply a lateral stress upon the chalcogenide material in response to a temperature change or an electrical field.

### Claim 18 (depends on 17)

The electronic device of claim 17, wherein the stress material is not in physical contact with the lower electrode.

### Claim 19 (depends on 17)

The electronic device of claim 17, wherein the stress material is in physical contact with the lower electrode.

### Claim 20 (depends on 17)

The electronic device of claim 17, wherein the lower electrode comprises a conductive member in electrical contact with a resistive heating element structured to generate heat as current flows through the resistive heating element during operation of the memory device.