# US 10,311,947 B2 · Via formation for cross-point memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,947 B2 - Document ID: US10311947B2 - Status: Granted - Kind: B2 - Application number: 15/280,238 - Filed: 2016-09-29 - Published: 2017-03-09 - Granted: 2019-06-04 - Earliest claimed: 2009-12-29 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Stephen Tang - Web page: https://patentgrep.com/patent/US10311947B2 ## CPC - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 13/003: {Cell access} - H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays} - H10N 70/066: {by filling of openings, e.g. damascene method} - H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect} - H10N 70/8265: {on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices} - H10N 70/841: {Electrodes} - H10W 20/20: Interconnections within wafers or substrates, e.g. through-silicon vias [TSV] - H10W 20/43: Layouts of interconnections - H10B 63/84: {arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays} - H10B 63/845: {the switching components being connected to a common vertical conductor} - H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography} - H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10B: ELECTRONIC MEMORY DEVICES - H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device. ## Claims ### Claim 1 A memory device, comprising: a first plurality of electrically conductive lines oriented in a first direction on a first level; a second plurality of electrically conductive lines oriented in a second direction on a second level; a first memory material configurable to store information and positioned between the first plurality of electrically conductive lines and the second plurality of electrically conductive lines; and a plurality of electrically conductive vias in contact with the first memory material and with the second plurality of electrically conductive lines, wherein each electrically conductive via is configured to carry signals between the second plurality of electrically conductive lines and circuitry below the first level. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the first memory material comprises a plurality of etched areas, and wherein each etched area of the plurality comprises a trench. ### Claim 3 (depends on 1) The memory device of claim 1, wherein the first memory material comprises an array of memory cells positioned between the first plurality of electrically conductive lines and the second plurality of electrically conductive lines. ### Claim 4 (depends on 3) The memory device of claim 3, wherein the array of memory cells comprises an array of selector devices positioned between the array of memory cells and the second plurality of electrically conductive lines. ### Claim 5 (depends on 3) The memory device of claim 3, wherein the first plurality of electrically conductive lines comprise word-lines operatively coupled to the array of memory cells. ### Claim 6 (depends on 3) The memory device of claim 3, wherein the second plurality of electrically conductive lines comprise bit-lines operatively coupled to the array of memory cells. ### Claim 7 A memory device, comprising: a first plurality of electrically conductive lines oriented in a first direction on a first level; a second plurality of electrically conductive lines oriented in a second direction on a second level; and a first memory material configurable to store information positioned between the first plurality of electrically conductive lines and the second plurality of electrically conductive lines; and a plurality of electrically conductive vias in contact with the first memory material and with the second plurality of electrically conductive lines, wherein each electrically conductive via is configured to carry signals between the second plurality of electrically conductive lines and circuitry below the first level, and wherein at least one via of the plurality of electrically conductive vias is located within a trench of one etched area of a plurality of etched areas filled with an electrically conductive material. ### Claim 8 A system, comprising: a non-volatile memory device, comprising: a first plurality of electrically conductive lines oriented in a first direction on a first level; a second plurality of electrically conductive lines oriented in a second direction on a second level; a first memory material configurable to store information and positioned between the first plurality of electrically conductive lines and the second plurality of electrically conductive lines; a plurality of electrically conductive vias in contact with the first memory material and with the second plurality of electrically conductive lines, wherein each electrically conductive via is configured to carry signals between the second plurality of electrically conductive lines and circuitry below the first level; and a control unit to access an array of memory cells in response to receiving a memory access command; and a processor to transmit the memory access command to the non-volatile memory device, the processor further to execute one or more applications stored in the array of memory cells. ### Claim 9 (depends on 8) The system of claim 8, wherein the array of memory cells comprises an array of phase change memory cells in a cross-point array. ### Claim 10 (depends on 9) The system of claim 9, wherein the cross-point array comprises a layer of selector devices positioned above the array of phase change memory cells and below the second plurality of electrically conductive lines. ### Claim 11 (depends on 8) The system of claim 8, wherein each of the plurality of electrically conductive vias is positioned at a location where one of the second plurality of electrically conductive lines overlaps with one of the first plurality of electrically conductive lines. ### Claim 12 A memory device, comprising: a first plurality of electrically conductive electrode lines oriented in a first direction on a first level; and a first memory material configurable to store information and positioned over the first plurality of electrically conductive electrode lines, the first memory material configurable to store information and including a plurality of electrically conductive vias in contact with the first memory material and with a second plurality of electrically conductive lines oriented in a second direction on a second level, wherein each electrically conductive via of the plurality of electrically conductive vias is configured to carry signals between the second plurality of electrically conductive lines and circuitry below the first level. ### Claim 13 (depends on 12) The memory device of claim 12, wherein the plurality of electrically conductive vias extend from the first plurality of electrically conductive electrode lines to the second plurality of electrically conductive electrode lines to operatively couple the first plurality of electrically conductive electrode lines and the second plurality of electrically conductive electrode lines. ### Claim 14 (depends on 12) The memory device of claim 12, further comprising of the memory material over the second plurality of electrically conductive electrode lines, the memory device comprising multiple stacks of cross-point memory arrays. ### Claim 15 (depends on 12) The memory device of claim 12, further comprising a selector material between the first plurality of electrically conductive electrode lines and the second plurality of electrically conductive electrode lines. ### Claim 16 (depends on 15) The memory device of claim 15, wherein each of the plurality of electrically conductive vias is in contact with the selector material. ### Claim 17 (depends on 15) The memory device of claim 15, wherein the selector material comprises a plurality of patterned line segments, wherein each of the plurality of patterned line segments is oriented orthogonal to the first plurality of electrically conductive electrode lines, wherein each of the plurality of electrically conductive vias is located within one of the plurality of patterned line segments. ### Claim 18 (depends on 12) The memory device of claim 12, wherein a sidewall of each of the plurality of electrically conductive vias is defined by a sidewall of the first memory material. ### Claim 19 (depends on 12) The memory device of claim 12, wherein a sidewall of each of the plurality of electrically conductive vias is aligned with a sidewall of one of the first plurality of electrically conductive electrode lines.