# US 10,311,945 B2 · Semiconductor device with a plurality of surrounding gate transistors

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- Number: US 10,311,945 B2
- Document ID: US10311945B2
- Status: Granted
- Kind: B2
- Application number: 14/886,637
- Filed: 2015-10-19
- Published: 2016-02-11
- Granted: 2019-06-04
- Earliest claimed: 2013-10-23
- Assignees: Unisantis Electronics Singapore Pte. Ltd.
- Applicants: Unisantis Electronics Singapore Pte. Ltd.
- Inventors: Fujio Masuoka; Masamichi Asano
- Web page: https://patentgrep.com/patent/US10311945B2

## CPC

- G11C 11/418: Address circuits
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 8/10: Decoders
- H10B 10/12: {comprising a MOSFET load element}
- H10B 10/125: {the MOSFET being a thin film transistor [TFT]}
- H10B 10/18: {Peripheral circuit regions}
- H10D 30/63: Vertical IGFETs (H10D30/66 {, H10D30/6728, H10D30/689, H10D30/693} take precedence)
- H10D 30/6735: {having gates fully surrounding the channels, e.g. gate-all-around}
- H10D 62/83: being Group IV materials, e.g. B-doped Si or undoped Ge
- H10D 64/512: {Disposition of the gate electrodes, e.g. buried gates}
- H10D 84/0195: {the components including vertical IGFETs}
- H10D 84/038: {using silicon technology, e.g. SiGe}
- H10D 84/85: Complementary IGFETs, e.g. CMOS
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES

## Abstract

A semiconductor device constituting a decoder circuit for memory selection and having a smaller area is provided by using surrounding gate transistors (SGTs), which are vertical transistors. In a decoder circuit formed by a plurality of MOS transistors arranged in m rows and n columns, the MOS transistors that constitute the decoder circuit are arranged on a planar silicon layer formed on a substrate. Each has a structure including a drain, a gate, and a source arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer is formed by a first active region of a first conductivity type and a second active region of a second conductivity type, and the regions are connected to each other via a silicide layer formed on the surface of the planar silicon layer. Consequently, a semiconductor device that constitutes a decoder circuit having a smaller area is provided.

## Claims

### Claim 1

A semiconductor device forming a decoder circuit, comprising:
a plurality of rows each row including a NAND decoder connected to an inverter, each NAND decoder including a plurality of transistors on a substrate in M rows and N columns, each of the plurality of transistors having a source, a drain, and a gate in layers arranged in a direction perpendicular to the substrate;
each of the plurality of transistors including:
a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region arranged on a top or on a bottom of the silicon pillar; and
a drain region arranged on the top or on the bottom of the silicon pillar, on a side of the silicon pillar opposite from the source region;
each NAND decoder including i P-channel MOS transistors, and i N-channel MOS transistors, where i=3 or 4, and wherein in the i P-channel MOS transistors and the i N-channel MOS transistors, a k-th P-channel MOS transistor, where k=1 to 4, and a k-th N-channel MOS transistor constitute a pair, and the gate of the k-th P-channel MOS transistor and the gate of the k-th N-channel MOS transistor are connected to each other;
the drain regions of the i P-channel MOS transistors and the drain region of a first N-channel MOS transistor are arranged on a side of the silicon pillars closer to the substrate, and the drain regions of the i P-channel MOS transistors and the drain region of the first N-channel MOS transistor are connected to one another via a silicide region;
the source region of an s-th N-channel MOS transistor, where s=1 to n−1, and the drain region of an s+1-th N-channel MOS transistor are connected to each other via a connection including a silicide region;
the source regions of the i P-channel MOS transistors are each connected to a supply voltage line, and the source region of an i-th N-channel MOS transistor is connected to a reference voltage line;
the gates of k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are connected to input signal lines, where the gate of the first N-channel MOS transistor is connected to a same signal line as a first P-channel MOS transistor and gates of a second and a third P-channel transistor are each connected to a different signal line than the gate of the first N-channel MOS transistor; and
the supply voltage line, the reference voltage line, and the input signal lines extend in an identical direction.

### Claim 2 (depends on 1)

The semiconductor device according to claim 1, wherein the i P-channel MOS transistors are arranged in one row and n columns, the i N-channel MOS transistors are arranged in one row and n columns, and the supply voltage line, the reference voltage line, and the input signal lines extend in a direction perpendicular to a row direction.

### Claim 3 (depends on 2)

The semiconductor device according to claim 2, wherein the source regions of the i P-channel MOS transistors are connected to a first metal line, the source region of an N-channel MOS transistor in an n-th column is connected to another first metal line, the supply voltage line and the reference voltage line that extend perpendicular to the row are constituted by second metal lines, and the source regions of the i P-channel MOS transistors are connected to one of the second metal lines via the first metal line, and the source region of the N-channel MOS transistor in the n-th column is connected to the other of the second metal lines via the other first metal line.

### Claim 4 (depends on 2)

The semiconductor device according to claim 2, wherein the input signal lines that extend perpendicular to the row are constituted by second metal lines, and the gates of the k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are connected to the second metal lines via first metal lines that extend in the row direction.

### Claim 5 (depends on 2)

The semiconductor device according to claim 2, wherein the decoder circuit further comprises a first inverter arranged along the MOS transistors having the two-row N-column arrangement the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first column being connected in common to one another, are connected to input of the first inverter, and output of the first inverter serves as output of the decoder circuit.

### Claim 6

A semiconductor device forming a decoder circuit, comprising:
a plurality of rows each row including a NAND decoder connected to an inverter, each NAND decoder including a plurality of transistors arranged on a substrate in M rows and N columns, each of the plurality of transistors having a source, a drain, and a gate in layers arranged in a direction perpendicular to the substrate;
each of the plurality of transistors including:
a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region arranged on a top or on a bottom of the silicon pillar; and
a drain region on the top or on the bottom of the silicon pillar, on a side of the silicon pillar opposite from the source region;
each NAND decoder including i P-channel MOS transistors, and i N-channel MOS transistors, where i=3 or 4, and wherein in the i P-channel MOS transistors and the i N-channel MOS transistors, a k-th P-channel MOS transistor, where k=1 to n 4, and a k-th N-channel MOS transistor constitute a pair, and the gate of the k-th P-channel MOS transistor and the gate of the k-th N-channel MOS transistor are connected to each other;
the drain regions of the i P-channel MOS transistors and the drain region of a first N-channel MOS transistor are arranged on a side of the silicon pillars closer to the substrate, and the drain regions of the i P-channel MOS transistors and the drain region of the first N-channel MOS transistor are connected to one another via a silicide region;
the source region of an s-th N-channel MOS transistor, where s=1 to i−1, and the drain region of an s+1-th N-channel MOS transistor are connected to each other via a connection including a silicide region;
the source regions of the i P-channel MOS transistors are each connected to a supply voltage line, and the source region of an i-th N-channel MOS transistor is connected to a reference voltage line;
the gates of k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are connected to input signal lines, where the gate of a first N-channel MOS transistor is connected to a same signal line as a first P-channel MOS transistor and gates of a second and a third P-channel transistor are each connected to a different signal line than the gate of the first N-channel MOS transistor; and
the supply voltage line, the reference voltage line, and the input signal lines extend in an identical direction,
wherein the i P-channel MOS transistors are arranged in M rows and one column, the i N-channel MOS transistors are arranged in M rows and one column, and the supply voltage line, the reference voltage line, and the input signal lines extend in a direction perpendicular to a row direction.

### Claim 7 (depends on 6)

The semiconductor device according to claim 6, wherein the source regions of the i P-channel MOS transistors are connected to a first metal line, the source region of an N-channel MOS transistor in an M-th row is connected to another first metal line, the supply voltage line and the reference voltage line that extend perpendicular to the rows are constituted by second metal lines, and the source regions of the i P-channel MOS transistors are connected to one of the second metal lines via the first metal line, and the source region of the N-channel MOS transistor in the M-th row is connected to the other of the second metal lines via the other first metal line.

### Claim 8 (depends on 6)

The semiconductor device according to claim 6, wherein the input signal lines that extend perpendicular to the rows are constituted by second metal lines, and the gates of the k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are connected to the second metal lines via first metal lines that extend in a direction parallel to the rows.

### Claim 9 (depends on 6)

The semiconductor device according to claim 6, wherein the decoder circuit further comprises a first inverter arranged along the MOS transistors having the one-row N-column arrangement the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first row being connected in common to one another, are connected to input of the first inverter, and output of the first inverter serves as output of the decoder circuit.

### Claim 10

A semiconductor device forming a decoder circuit, comprising:
a plurality of rows each row including a NAND decoder connected to an inverter, each NAND decoder including a plurality of transistors on a substrate in M rows and N columns, each of the plurality of transistors having a source, a drain, and a gate in layers in a direction perpendicular to the substrate;
each of the plurality of transistors including:
a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region arranged on a top or on a bottom of the silicon pillar, and
a drain region arranged on the top or on the bottom of the silicon pillar, on a side of the silicon pillar opposite to the source region:
each NAND decoder including i P-channel MOS transistors, and i N-channel MOS transistors, where i=3 or 4, and wherein in the i P-channel MOS transistors and the i N-channel MOS transistors, a k-th P-channel MOS transistor, where k=1 to, and a k-th N-channel MOS transistor constitute a pair, and the gate of the k-th P-channel MOS transistor and the gate of the k-th N-channel MOS transistor are connected to each other,
the source regions of the i P-channel MOS transistors and the source region of a first N-channel MOS transistor are arranged on a side of the silicon pillars closer to the substrate, and the drain regions of the i P-channel MOS transistors and the drain region of the first N-channel MOS transistor are connected to one another via contacts,
the source region of an s-th N-channel MOS transistor, where s=1 to i−1, and the drain region of an s+1-th N-channel MOS transistor are connected to each other,
the source regions of the i P-channel MOS transistors are each connected to a supply voltage line, and the source region of an i-th N-channel MOS transistor is connected to a reference voltage line, the gates of k pairs of MOS transistors,
the gates of each pair of MOS transistors being connected to each other, are connected to input signal lines, and the supply voltage line, the reference voltage line, and the input signal lines extend in an identical direction, where the gate of a first N-channel MOS transistor is connected to a same signal line as a first P-channel MOS transistor and gates of a second and a third P-channel transistor are each connected to a different signal line than the gate of the first N-channel MOS transistor,
and the supply voltage line, the reference voltage line, and the input signal lines extend in an identical direction,
wherein the source regions of P-channel MOS transistors adjacent to each other in the decoder circuit are connected in common via a silicide region.

### Claim 11 (depends on 10)

The semiconductor device according to claim 10, wherein the i P-channel MOS transistors are arranged in one row and n columns, the i N-channel MOS transistors are arranged in one row and n columns, and the supply voltage line, the reference voltage line, and the input signal lines extend in a direction perpendicular to a row direction.

### Claim 12 (depends on 11)

The semiconductor device according to claim 11, wherein the source regions of the i P-channel MOS transistors are connected to a first metal line that extends in a direction parallel to the row, the source region of an N-channel MOS transistor in an N-th column is connected to another first metal line, the supply voltage line and the reference voltage line that extend perpendicular to the row are constituted by second metal lines, and the source regions of the i P-channel MOS transistors are connected to one of the second metal lines via the first metal line, and the source region of the N-channel MOS transistor in the n-th column is connected to the other of the second metal lines via the other first metal line.

### Claim 13 (depends on 11)

The semiconductor device according to claim 11, wherein the input signal lines that extend perpendicular to the row are constituted by second metal lines, and the gates of the k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are connected to the second metal lines via first metal lines that extend in the row direction.

### Claim 14 (depends on 11)

The semiconductor device according to claim 11, wherein a plurality of the decoder circuits are arranged in a column direction.

### Claim 15 (depends on 11)

The semiconductor device according to claim 11, wherein the decoder circuit further comprises a first inverter arranged along the MOS transistors having the one-row n-column arrangement the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first column being connected in common to one another via contacts, are connected to input of the first inverter, and output of the first inverter serves as output of the decoder circuit.

### Claim 16 (depends on 15)

The semiconductor device according to claim 15, wherein the first inverter includes at least an n+1-th P-channel MOS transistor, and an n+1-th N-channel MOS transistor, the source regions of the i P-channel MOS transistors and the source region of the n+1-th P-channel MOS transistor are connected in common via a silicide region, and are connected to a first metal line, the source region of the N-channel MOS transistor in the n-th column and the source region of the n+1-th N-channel MOS transistor are connected in common via a silicide region, and are connected to another first metal line, the supply voltage line and the reference voltage line that extend perpendicular to the row are constituted by second metal lines, and the source regions of the i P-channel MOS transistors are connected to one of the second metal lines via the first metal line, and the source region of the N-channel MOS transistor in the n-th column is connected to the other of the second metal lines via the other first metal line.

### Claim 17

A semiconductor device forming a decoder circuit, comprising:
a plurality of rows each row including a NAND decoder connected to an inverter, each NAND decorder including a plurality of transistors arranged on a substrate in M rows and N columns, each of the plurality of transistors having a source, a drain, and a gate in layers in a direction perpendicular to the substrate;
each of the plurality of transistors including:
a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region arranged on a top or on a bottom of the silicon pillar, and a drain region arranged on the top or on the bottom of the silicon pillar, on a side of the silicon pillar opposite to the source region:
each NAND decoder including i P-channel MOS transistors, and i N-channel MOS transistors, where i=3 or 4, and wherein in the i P-channel MOS transistors and the i N-channel MOS transistors, a k-th P-channel MOS transistor, where k=1 to, and a k-th N-channel MOS transistor constitute a pair, and the gate of the k-th P-channel MOS transistor and the gate of the k-th N-channel MOS transistor are connected to each other,
the source regions of the i P-channel MOS transistors and the source region of a first N-channel MOS transistor are arranged on a side of the silicon pillars closer to the substrate, and the drain regions of the i P-channel MOS transistors and the drain region of the first N-channel MOS transistor are connected to one another via contacts,
the source region of an s-th N-channel MOS transistor, where s=1 to n−1, and the drain region of an s+1-th N-channel MOS transistor are connected to each other,
the source regions of the i P-channel MOS transistors are each connected to a supply voltage line, and the source region of an n-th N-channel MOS transistor is connected to a reference voltage line,
the gates of k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are connected to input signal lines, where the gate of a first N-channel MOS transistor is connected to a same signal line as a first P-channel MOS transistor and gates of a second and a third P-channel transistor are each connected to a different signal line than the gate of the k first N-channel MOS transistor, and
the supply voltage line, the reference voltage line, and the input signal lines extend in an identical direction,
wherein the i P-channel MOS transistors are arranged in M rows and one column, the i N-channel MOS transistors are arranged in M rows and one column, and the supply voltage line, the reference voltage line, and the input signal lines extend in a direction perpendicular to a row direction,
wherein the source regions of P-channel MOS transistors adjacent to each other in the decoder circuit are connected in common via a silicide region.

### Claim 18 (depends on 17)

The semiconductor device according to claim 17, wherein the source regions of the i P-channel MOS transistors are connected to a first metal line, the source region of an N-channel MOS transistor in an M-th row is connected to another first metal line, the supply voltage line and the reference voltage line that extend perpendicular to the rows are constituted by second metal lines, and the source regions of the n P-channel MOS transistors are connected to one of the second metal lines via the first metal line, and the source region of the N-channel MOS transistor in the n-th row is connected to the other of the second metal lines via the other first metal line.

### Claim 19 (depends on 17)

The semiconductor device according to claim 17, wherein the input signal lines that extend perpendicular to the row direction are constituted by second metal lines, and the gates of the k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are connected to the second metal lines via first metal lines that extend in a direction along the rows.

### Claim 20 (depends on 17)

The semiconductor device according to claim 17, wherein the decoder circuit further comprises a first inverter having a one-row and two-column arrangement, the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first row being connected in common to one another via contacts, are connected to an input of the first inverter, and an output of the first inverter serves as an output of the decoder circuit.

### Claim 21 (depends on 20)

The semiconductor device according to claim 20, wherein the first inverter includes at least an n+1-th P-channel MOS transistor, and an i+1-th N-channel MOS transistor, the source regions of the i P-channel MOS transistors and the source region of the n+1-th P-channel MOS transistor are connected in common via a silicide region, and are connected to a first metal line, the source region of the N-channel MOS transistor in the M-th row and the source region of the n+1-th N-channel MOS transistor are connected in common via a silicide region, and are connected to another first metal line, the supply voltage line and the reference voltage line that extend perpendicular to the rows are constituted by second metal lines, and the source regions of the i P-channel MOS transistors are connected to one of the second metal lines via the first metal line, and the source region of the N-channel MOS transistor in the n-th row is connected to the other of the second metal lines via the other first metal line.

### Claim 22

A semiconductor device forming a static memory including a plurality of transistors arranged on a substrate, each of the plurality of transistors having a source, a drain, and a gate in layers in a direction perpendicular to the substrate, the static memory comprising:
a plurality of static memory cells each including at least six MOS transistors arranged on an insulating film formed on the substrate and arranged in a matrix;
a plurality of row address circuits each specifying one row-line of the static memory cells; and
a plurality of row decoder circuits each including a plurality of MOS transistors and each selecting one row of the static memory cells in accordance with signals from the row address circuits;
each of the six MOS transistors that constitute each of the static memory cells, and each of the plurality of MOS transistors that constitute each of the row decoder circuits including:
a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region arranged on a top or on a bottom of the silicon pillar, and a drain region arranged on the top or on the bottom of the silicon pillar, on a side of the silicon pillar opposite from source region, the six MOS transistors included in each of the static memory cells being arranged in two rows and three columns, each of the row decoder circuits including at least n P-channel MOS transistors arranged in one row and N columns, i N-channel MOS transistors arranged in one row and N columns, and an inverter,
wherein, in the i P-channel MOS transistors and the i N-channel MOS transistors, a P-channel MOS transistor in a k-th column, where k=1 to n and n=2 to 4, arranged in one row and an N-channel MOS transistor in the k-th column arranged in one row constitute a pair, and the gate of the P-channel MOS transistor in the k-th column and the gate of the N-channel MOS transistor in the k-th column are connected to each other, the drain regions of the i P-channel MOS transistors and the drain region of an N-channel MOS transistor in a first column are arranged on a side of the silicon pillars closer to the substrate, and the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first column are connected to one another via a silicide region, the source region of an N-channel MOS transistor in an s-th column, where s=1 to n−1, and the drain region of an N-channel MOS transistor in an s+1-th column are connected to each other, the source regions of the i P-channel MOS transistors are each connected to a supply voltage line that extends in a direction perpendicular to the row, and the source region of an N-channel MOS transistor in an N-th column is connected to a reference voltage line that extends in the direction perpendicular to the row, input signal lines that are connected to the gates of k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are constituted by lines that extend in the direction perpendicular to the row, and the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first column are connected to an input gate of the inverter, and output of the inverter is connected to a row selection line of the static memory cells.

### Claim 23 (depends on 22)

The semiconductor device according to claim 22, wherein the source regions of the i P-channel MOS transistors are connected to a first metal line, the source region of the N-channel MOS transistor in the N-th column is connected to another first metal line, the supply voltage line and the reference voltage line that extend perpendicular to the row are constituted by second metal lines, the source regions of the i P-channel MOS transistors are connected to one of the second metal lines via the first metal line, and the source region of the N-channel MOS transistor in the N-th column is connected to the other of the second metal lines via the other first metal line, the input signal lines that extend perpendicular to the row are constituted by second metal lines, and the gates of the k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are connected to the second metal lines via first metal lines that extend in a direction along the row.

### Claim 24

A semiconductor device forming a static memory including a plurality of transistors arranged on a substrate, each of the plurality of transistors having a source, a drain, and a gate arranged in layers in a direction perpendicular to the substrate, the static memory comprising:
a plurality of static memory cells each including at least six MOS transistors arranged on an insulating film formed on the substrate and arranged in a matrix;
a plurality of row address circuits each specifying one row-line of the static memory cells; and
a plurality of row decoder circuits each including a plurality of MOS transistors and each selecting one row of the static memory cells in accordance with signals from the row address circuits, each of the six MOS transistors that constitute each of the static memory cells, and each of the plurality of MOS transistors that constitute each of the row decoder circuits including a silicon pillar, an insulator surrounding a side surface of the silicon pillar, a gate surrounding the insulator, a source region arranged on a top or on a bottom of the silicon pillar, and a drain region arranged on the top or on the bottom of the silicon pillar, on a side of the silicon pillar opposite from the source region, the six MOS transistors included in each of the static memory cells being arranged in two rows and three columns, each of the row decoder circuits including at least n P-channel MOS transistors arranged in one row and N columns, n N-channel MOS transistors arranged in one row and N columns, and an inverter,
wherein, in the i P-channel MOS transistors and the i N-channel MOS transistors, a P-channel MOS transistor in a k-th column, where k=1 to n and n=2 to 4, arranged in one row and an N-channel MOS transistor in the k-th column arranged in one row constitute a pair, and the gate of the P-channel MOS transistor in the k-th column and the gate of the N-channel MOS transistor in the k-th column are connected to each other, the source regions of the i P-channel MOS transistors and the source region of an N-channel MOS transistor in a first column are arranged on a side of the silicon pillars closer to the substrate, and the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first column are connected to one another via contacts, the source region of an N-channel MOS transistor in an s-th column, where s=1 to n−1, and the drain region of an N-channel MOS transistor in an s+1-th column are connected to each other, the source regions of the i P-channel MOS transistors are each connected to a supply voltage line that extends in a direction perpendicular to the row, and the source region of an N-channel MOS transistor in an N-th column is connected to a reference voltage line that extends in the direction perpendicular to the row, input signal lines that are connected to the gates of n pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are constituted by lines that extend in the direction perpendicular to the row, and the drain regions of the i P-channel MOS transistors and the drain region of the N-channel MOS transistor in the first column are connected to an input gate of the inverter, and output of the inverter is connected to a row selection line of the static memory cells.

### Claim 25 (depends on 24)

The semiconductor device according to claim 24, wherein the source regions of the i P-channel MOS transistors are connected to a first metal line that extends in a direction parallel to the row, the source region of the N-channel MOS transistor in the N-th column is connected to another first metal line, the supply voltage line and the reference voltage line that extend perpendicular to the row are constituted by second metal lines, the source regions of the i P-channel MOS transistors are connected to one of the second metal lines via the first metal line, and the source region of the N-channel MOS transistor in the N-th column is connected to the other of the second metal lines via the other first metal line, the input signal lines that extend perpendicular to the row are constituted by second metal lines, and the gates of the k pairs of MOS transistors, the gates of each pair of MOS transistors being connected to each other, are connected to the second metal lines via first metal lines that extend in a direction along the row.