# US 10,311,943 B2 · Semiconductor integrated circuit device and wearable device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,943 B2 - Document ID: US10311943B2 - Status: Granted - Kind: B2 - Application number: 15/888,426 - Filed: 2018-02-05 - Published: 2018-06-07 - Granted: 2019-06-04 - Earliest claimed: 2014-12-17 - Assignees: Renesas Electronics Corporation - Applicants: Renesas Electronics Corporation - Inventors: Shiro Kamohara; Yasushi Yamagata; Takumi Hasegawa; Nobuyuki Sugii - Web page: https://patentgrep.com/patent/US10311943B2 ## CPC - G11C 11/417: for memory cells of the field-effect type - G04G 21/025: {for measuring physiological data} - G11C 5/146: {Substrate bias generators (G11C5/141 takes precedence)} - H04B 1/385: {Transceivers carried on the body, e.g. in helmets} - H10B 10/12: {comprising a MOSFET load element} - H10B 10/18: {Peripheral circuit regions} - H10D 84/85: Complementary IGFETs, e.g. CMOS - H10D 86/201: {the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence)} - H10D 87/00: Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate - G11C 5/148: {Details of power up or power down circuits, standby circuits or recovery circuits} - G11C: STATIC STORES (semiconductor memory devices H10B) - G04G: ELECTRONIC TIME-PIECES - H04B: TRANSMISSION - H10B: ELECTRONIC MEMORY DEVICES - H10D: INORGANIC ELECTRIC SEMICONDUCTOR DEVICES ## Abstract To provide a semiconductor device which can be stably operated while achieving a reduction of the power consumption. A semiconductor device includes a CPU, a system controller which designates an operation speed of the CPU, P-type SOTB transistors, and N-type SOTB transistors. The semiconductor device is provided with an SRAM which is connected to the CPU, and a substrate bias circuit which is connected to the system controller and is capable of supplying substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. Here, when the system controller designates a low speed mode to operate the CPU at a low speed, the substrate bias circuit supplies the substrate bias voltages to the P-type SOTB transistors and the N-type SOTB transistors. ## Claims ### Claim 1 A semiconductor integrated circuit device comprising: a memory cell array which includes: a plurality of memory cells, each of the memory cells having a P-type SOTB transistor and an N-type SOTB transistor; a plurality of word lines coupled to the memory cells, respectively; and a plurality of bit lines coupled to the memory cells, respectively; a plurality of word drivers coupled to the word lines respectively, each of the word drivers having a P-type MOS transistor and an N-type MOS transistor, wherein the semiconductor integrated circuit has a first mode and a second mode, wherein a first voltage is supplied to a substrate of the P-type SOTB transistor, a second voltage is supplied to a substrate of the N-type SOTB transistor, a third voltage is supplied to a substrate of the P-type MOS transistor, and a fourth voltage is supplied to a substrate of the N-type MOS transistor when the semiconductor integrated circuit is in the first mode, and wherein an operating frequency of the first mode is lower than that of the second mode. ### Claim 2 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein the first and second voltages are not supplied to the substrates of the P-type and the N-type SOTB transistors when the semiconductor integrated circuit is in the second mode. ### Claim 3 (depends on 1) The semiconductor integrated circuit device according to claim 1, further comprising: a substrate bias generation circuit supplying the first, second, third and fourth voltages. ### Claim 4 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein a static random access memory circuit includes the memory cell array and the word drivers and is coupled to a central processing unit via a bus, wherein the central processing unit has a P-type MOS transistor and an N-type MOS transistor, and wherein the third voltage is supplied to a substrate of the P-type MOS transistor of the central processing unit, and the fourth voltage is supplied to a substrate of the N-type MOS transistor of the central processing unit when the semiconductor integrated circuit is in the first mode. ### Claim 5 (depends on 4) The semiconductor integrated circuit device according to claim 4, further comprising: a mode designation circuit for selecting the first mode and the second mode based on a designation signal from the central processing unit. ### Claim 6 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein a value of the first voltage is different from a value of the second voltage, and wherein a value of the third voltage is different from a value of the fourth voltage. ### Claim 7 (depends on 1) The semiconductor integrated circuit device according to claim 1, wherein the P-type SOTB transistor includes a gate electrode, a source region, a drain region, a channel region which forms a channel between the source region and the drain region, and a first region which faces the channel through an insulation film, wherein a first substrate bias voltage is supplied to the first region, wherein the N-type SOTB transistor includes a gate electrode, a source region, a drain region, a channel region which forms a channel between the source region and the drain region, and a second region which faces the channel through an insulation film, and wherein a second substrate bias voltage is supplied to the second region. ### Claim 8 (depends on 1) A wearable device comprising the semiconductor integrated circuit device according to claim 1.