Apparatuses and methods for input signal receiver circuits

An apparatus, comprising:

• an amplifier circuit configured to receive a reference voltage and an input signal, the amplifier circuit configured to provide an output having a same logic level to the input signal;
• a latch circuit configured to latch the output of the amplifier circuit and provide a first latched logic level and a second latched logic level complementary to the first latched logic level;
• a pull-up circuit configured to provide a resistive coupling between a power supply providing a high logic level voltage and a common node;
• and
• a pull-down circuit configured to provide a low logic level voltage to the common node when activated by the second latched logic level.

An apparatus, comprising:

• a first amplifier circuit configured to receive a reference voltage and an input signal and configured to receive a first enable signal, the first amplifier circuit further configured to provide a first output having a logic level based on a voltage of the input signal relative to the reference voltage when activated by the first enable signal and to provide a logic level voltage when not activated by the first enable signal;
• a second amplifier circuit configured to receive the reference voltage and the input signal and configured to receive a second enable signal, the second amplifier circuit further configured to provide a second output having a logic level based on a voltage of the input signal relative to the reference voltage when activated by the second enable signal, wherein the second output is complementary to the first output when both the first and second amplifier circuits are activated;
• an inverter circuit configured to provide an output that is complementary to the logic level of the first output;
• a first transistor configured to provide a high logic level voltage to a common node when activated by the output from the inverter circuit, wherein the first transistor is activated by the complement of the logic level voltage when the first amplifier circuit is not activated;
• and
• a second transistor configured to provide a low logic level voltage to the common node when activated by the second output.