# US 10,311,940 B2 · Nullifying incorrect sampled data contribution in decision feedback equalizer at restart of forwarded clock in memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,940 B2 - Document ID: US10311940B2 - Status: Granted - Kind: B2 - Application number: 15/850,311 - Filed: 2017-12-21 - Published: 2018-04-26 - Granted: 2019-06-04 - Earliest claimed: 2015-12-04 - Assignees: Integrated Device Technology, Inc. - Applicants: Integrated Device Technology, Inc. - Inventors: Craig DeSimone; Praveen Singh - Web page: https://patentgrep.com/patent/US10311940B2 ## CPC - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G06F 1/04: Generating or distributing clock signals or signals derived directly therefrom - G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports - G11C 7/1066: {Output synchronization} - G11C 7/1093: {Input synchronization} - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - H04L 25/03057: {with a recursive structure (H04L25/03031 takes precedence)} - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract An apparatus includes a receiver circuit and a data buffer. The receiver circuit may comprise a decision feedback equalizer (DFE). The data buffer circuit may be configured to initialize a condition of the receiver circuit in response to a control signal prior to reception of a command sequence associated with a directed access to a memory system. The control signal generally indicates detection of a non-consecutive clock associated with a start of the command sequence. The data buffer circuit may generate one or more tap enable signals configured to determine a number of clock cycles during which a contribution of one or more taps of the decision feedback equalizer (DFE) are delayed. ## Claims ### Claim 1 An apparatus comprising: a receiver circuit comprising a decision feedback equalizer (DFE); and a data buffer circuit configured to initialize a condition of said receiver circuit in response to a control signal prior to reception of a command sequence associated with a directed access to a memory system, wherein (i) said control signal indicates detection of a non-consecutive clock associated with a start of said command sequence and (ii) said data buffer circuit generates one or more tap enable signals configured to determine a number of clock cycles during which a contribution of one or more taps of said decision feedback equalizer (DFE) are delayed. ### Claim 2 (depends on 1) The apparatus according to claim 1, wherein said data buffer circuit initializes said receiver circuit by delaying said contributions of said one or more taps of said decision feedback equalizer (DFE) of said receiver circuit until a data value has been registered in a corresponding data flop of each of said one or more taps. ### Claim 3 (depends on 1) The apparatus according to claim 1, wherein said data buffer circuit initializes said receiver circuit by delaying said contributions of said one or more taps of said decision feedback equalizer (DFE) of said receiver circuit for a predetermined number of clock cycles. ### Claim 4 (depends on 1) The apparatus according to claim 1, wherein said data buffer circuit sets an output of said decision feedback equalizer to zero volts for a predetermined number of clock cycles in response to said control signal. ### Claim 5 (depends on 1) The apparatus according to claim 1, wherein said data buffer circuit comprises an enable signal generating circuit configured to generate said one or more tap enable signals based on a forwarded clock from an external device and said control signal. ### Claim 6 (depends on 5) The apparatus according to claim 5, wherein said enable signal generating circuit comprises a delay line comprising a plurality of delay elements, each configured to generate one of said tap enable signals. ### Claim 7 (depends on 6) The apparatus according to claim 6, wherein: when said control signal is in a first state, an output of each of said plurality of delay elements is set to a first logic level; and when said control signal is in a second state, a second logic level presented at an input of said delay line is passed along said delay elements of said delay line on each transition of said forwarded clock. ### Claim 8 (depends on 1) The apparatus according to claim 1, wherein said contributions of said one or more taps of said decision feedback equalizer are generated by respective amplifier circuits. ### Claim 9 (depends on 8) The apparatus according to claim 8, wherein said respective amplifier circuits are configured to present a weighted tap value in response to a first state of a corresponding tap enable signal and a null tap value in response to a second state of the corresponding tap enable signal. ### Claim 10 (depends on 1) The apparatus according to claim 1, wherein said control signal is generated by a finite state machine based upon one or more static configuration bits, contents of one or more mode registers, and command sequence information. ### Claim 11 A method of initializing a receiver circuit of a memory system comprising: generating a control signal indicating detection of a non-consecutive clock associated with a start of a command sequence associated with a directed access to said memory system; and prior to reception of a first data bit associated with said command sequence, generating one or more tap enable signals to determine a number of clock cycles a contribution of one or more taps of a decision feedback equalizer (DFE) of said receiver circuit are delayed. ### Claim 12 (depends on 11) The method according to claim 11, wherein said receiver circuit is initialized by delaying said contributions of said one or more taps of said decision feedback equalizer (DFE) until a data value has been registered in a corresponding data flop of each of said one or more taps. ### Claim 13 (depends on 11) The method according to claim 11, wherein said receiver circuit is initialized by delaying said contributions of said one or more taps of said decision feedback equalizer (DFE) for a predetermined number of clock cycles. ### Claim 14 (depends on 11) The method according to claim 11, wherein an output of said decision feedback equalizer (DFE) is set to zero volts for a predetermined number of clock cycles in response to said control signal. ### Claim 15 (depends on 11) The method according to claim 11, further comprising: generating said one or more tap enable signals using a delay line comprising a plurality of delay elements. ### Claim 16 (depends on 15) The method according to claim 15, wherein said tap enable signals are generated based on a forwarded clock from an external device and said control signal. ### Claim 17 (depends on 16) The method according to claim 16, further comprising: when said control signal is in a first state, setting an output of each of said plurality of delay elements to a first logic level. ### Claim 18 (depends on 17) The method according to claim 17, further comprising: when said control signal is in a second state, passing a second logic level presented at an input of said delay line along said delay elements of said delay line on each transition of said forwarded clock.