# US 10,311,939 B2 · Semiconductor memory device, method of controlling read preamble signal thereof, and data transmission system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,939 B2 - Document ID: US10311939B2 - Status: Granted - Kind: B2 - Application number: 16/205,006 - Filed: 2018-11-29 - Published: 2019-03-28 - Granted: 2019-06-04 - Earliest claimed: 2009-01-20 - Assignees: Longitude Licensing Limited - Applicants: Longitude Licensing Limited - Inventors: Atsuo Koshizuka - Web page: https://patentgrep.com/patent/US10311939B2 ## CPC - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 7/1051: {Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits} - G11C 7/1066: {Output synchronization} - G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories} - G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C 11/409: Read-write [R-W] circuits - G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches - G11C 15/00: Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores - G11C 15/04: using semiconductor elements - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A system, includes a controller comprising a plurality of first external terminals configured to supply a command and an address, and communicate a data, and communicate a strobe signal related to the data; and a semiconductor memory device including a plurality of second external terminals corresponding to the plurality of first external terminals, at least one of the plurality of first external terminals and at least one of the plurality of second external terminals each being capable of supplying an information specifying a length of a preamble of the strobe signal before the semiconductor memory device communicates the data between the controller and the semiconductor memory device, the semiconductor memory device further including a preamble register configured to be capable of storing the information. ## Claims ### Claim 1 A method for transferring data from a first semiconductor device to a second semiconductor device, the method comprising: transferring preamble length information from the second semiconductor device to the first semiconductor device; storing the preamble length information in a register in the first semiconductor device; transferring a clock signal from the second semiconductor device to the first semiconductor device; switching between a Delay Lock Loop (DLL) selection mode in which a DLL circuit is activated and a DLL non-selection mode in which the DLL circuit is not activated; transferring, from the first semiconductor device to the second semiconductor device, a preamble having a duration specified by the preamble length information followed by a toggle signal having a burst length; and transferring, from the first semiconductor device to the second semiconductor device, data in synchronization with the toggle signal; wherein in the DLL selection mode, transferring the toggle signal further comprises: phase adjusting the toggle signal to the clock signal using the DLL circuit; and in the DLL non-selection mode, transferring the toggle signal comprises: transferring the toggle signal with the clock signal as a reference. ### Claim 2 (depends on 1) The method of claim 1, wherein the register is a mode register. ### Claim 3 (depends on 1) The method of claim 1, wherein the first semiconductor device is a memory device and the data is read data. ### Claim 4 (depends on 1) The method of claim 1, wherein the preamble comprises a first logic level for the duration specified by the preamble length information. ### Claim 5 (depends on 4) The method of claim 4, wherein the first logic level is a low logic level. ### Claim 6 (depends on 1) The method of claim 1, wherein the first preamble length information is an integer multiple of the period of the clock signal. ### Claim 7 (depends on 1) The method of claim 1, further comprising transferring a postamble following the toggle signal from the first semiconductor device to the second semiconductor device. ### Claim 8 (depends on 1) The method of claim 1, wherein in the DLL non-selection mode, the method further comprises: transferring second preamble length information from the second semiconductor device to the first semiconductor device; storing the second preamble length information in the register; and wherein transferring the preamble comprises transferring a preamble having a duration specified by the second preamble length information. ### Claim 9 (depends on 8) The method of claim 8, wherein the second preamble length information is longer than the first preamble length information. ### Claim 10 A method for transferring data from a first semiconductor device to a second semiconductor device comprising: transferring first preamble length information from the second semiconductor device to the first semiconductor device; storing the first preamble length information in a register in the first semiconductor device; transferring a clock signal from the second semiconductor device to the first semiconductor device; transferring a preamble having a duration specified by the first preamble length information, wherein the preamble is followed by a toggle signal having a burst length and the preamble is transferred from the first semiconductor device to the second semiconductor device, wherein the toggle signal is phase adjusted to the clock signal using a Delay Lock Loop (DLL) circuit; and transferring data in synchronization with the toggle signal from the first semiconductor device to second semiconductor device.