# US 10,311,938 B2 · Compact system with memory and PMU integration > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,938 B2 - Document ID: US10311938B2 - Status: Granted - Kind: B2 - Application number: 15/430,747 - Filed: 2017-02-13 - Published: 2017-06-01 - Granted: 2019-06-04 - Earliest claimed: 2014-03-04 - Assignees: Apple Inc. - Applicants: Apple Inc. - Inventors: Sanjay Dabral - Web page: https://patentgrep.com/patent/US10311938B2 ## CPC - G11C 11/4074: Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits - G11C 5/147: {Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops (G11C5/141 takes precedence)} - G11C 7/02: with means for avoiding parasitic signals - G11C 14/0018: {whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor} - G11C 29/021: {in voltage or current generators} - H10W 20/496: {Capacitor integral with wiring layers} - H10W 44/501: {Inductive arrangements (H10W44/20 takes precedence)} - H10W 44/601: {Capacitive arrangements (H10W44/20 takes precedence)} - H10W 70/685: comprising multiple insulating layers - H10W 90/00: Package configurations - H10W 20/497: {Inductive arrangements or effects of, or between, wiring layers} - H10W 72/244: {relative to underlying supporting features, e.g. bond pads, RDLs or vias} - H10W 90/297: {characterised by the through-semiconductor vias [TSVs] in the stacked chips} - H10W 90/722: {between stacked chips} - H10W 90/724: {between a chip and a stacked insulating package substrate, interposer or RDL} - H10W 90/754: {between a chip and a stacked insulating package substrate, interposer or RDL} - G11C: STATIC STORES (semiconductor memory devices H10B) - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract One or more integrated circuits including at least one integrated circuit that is fabricated in a DRAM fabrication process. Capacitors in the DRAM-fabricated integrated circuit can be used for decoupling for logic components of the integrated circuits, and may be used for fine-grain on-chip PMUs. Embedded DRAM memories can be used instead of SRAM memories, with increased density and reduced leakage. More compact systems can be implemented using the integrated circuits. ## Claims ### Claim 1 A system comprising: a first integrated circuit comprising one or more logic circuit components, the first integrated circuit implemented on a first semiconductor die manufactured using a logic circuit fabrication process; and a second integrated circuit coupled to the first integrated circuit, wherein the second integrated circuit is manufactured using a dynamic random access memory (DRAM) fabrication process and is implemented on a second semiconductor die that is separate from the first semiconductor die, and the second integrated circuit comprises: a plurality of capacitors constructed on the second semiconductor die, wherein the plurality of capacitors are coupled to a plurality of power supply grids on the first integrated circuit to provide decoupling capacitance for the one or more logic circuit components on the first semiconductor die, wherein the plurality of supply grids comprise a local, switched power supply grid for power gating and a global, unswitched power supply grid; and a plurality of power management units on the second semiconductor die and configured to provide a power supply to respective ones of the one or more logic circuit components on the first integrated circuit, wherein each power management unit of the plurality of power management units comprises: a voltage regulator configured to generate the voltage on the power supply, wherein the voltage regulator comprises one or more second capacitors formed using the DRAM fabrication process; and a register that is programmable with a magnitude of the voltage to be generated by the voltage regulator, and wherein the register is changeable during use to change the magnitude. ### Claim 2 (depends on 1) The system as recited in claim 1 wherein the second integrated circuit further comprises a DRAM. ### Claim 3 (depends on 2) The system as recited in claim 2 wherein the DRAM is a cache for a main memory DRAM that is external to the second integrated circuit. ### Claim 4 (depends on 3) The system as recited in claim 3 further comprising a third integrated circuit coupled to the second integrated circuit, wherein the third integrated circuit is coupled to the main memory DRAM. ### Claim 5 (depends on 4) The system as recited in claim 4 wherein the third integrated circuit comprises a memory controller for the main memory DRAM. ### Claim 6 (depends on 4) The system as recited in claim 4 wherein the third integrated circuit further comprises a non-volatile memory. ### Claim 7 (depends on 2) The system as recited in claim 2 wherein the DRAM is a main memory for the system. ### Claim 8 (depends on 7) The system as recited in claim 7 further comprising a third integrated circuit including a non-volatile memory that is a backing store for the DRAM. ### Claim 9 (depends on 1) The system as recited in claim 1 wherein the first integrated circuit and the second integrated circuit are packaged in a multi-chip module. ### Claim 10 An apparatus comprising: a first integrated circuit comprising one or more logic circuit components, the first integrated circuit implemented on a first semiconductor die manufactured using a logic circuit fabrication process; and a second integrated circuit coupled to the first integrated circuit, wherein the second integrated circuit is manufactured using a dynamic random access memory (DRAM) fabrication process and is implemented on a second semiconductor die that is separate from the first semiconductor die, and the second integrated circuit comprises: a plurality of capacitors constructed on the second semiconductor die, wherein the plurality of capacitors are coupled to a plurality of power supply grids on the first integrated circuit to provide decoupling capacitance for the one or more logic circuit components on the first semiconductor die, wherein the plurality of supply grids comprise a local switched power supply grid for power gating and a global unswitched power supply grid; and a plurality of power management units, wherein each power management unit comprises: a voltage regulator configured to generate a voltage on a power supply for the first integrated circuit, wherein the voltage regulator comprises one or more second capacitors formed using the DRAM fabrication process; and a register that is programmable with a magnitude of the voltage to be generated by the voltage regulator, and wherein the register is changeable during use to change the magnitude. ### Claim 11 (depends on 10) The apparatus as recited in claim 10 wherein the plurality of power management units (PMUs) are coupled to the one or more logic circuit components. ### Claim 12 (depends on 10) The apparatus as recited in claim 10 wherein the second integrated circuit further comprises a DRAM. ### Claim 13 (depends on 12) The apparatus as recited in claim 12 wherein the DRAM is a cache for a main memory DRAM that is external to the second integrated circuit. ### Claim 14 (depends on 12) The apparatus as recited in claim 12 wherein the DRAM is a main memory for a system that includes the apparatus. ### Claim 15 (depends on 10) The apparatus as recited in claim 10 wherein the first integrated circuit and the second integrated circuit are packaged together in an integrated circuit package. ### Claim 16 A system comprising: a plurality of integrated circuits included in an integrated circuit package, wherein: at least a first integrated of the plurality of integrated circuits is manufactured using a dynamic random access memory (DRAM) fabrication process; at least a second integrated circuit of the plurality of integrated circuits is fabricated using a different fabrication process than the DRAM fabrication process, wherein the first integrated circuit is implemented on a first semiconductor die and the second integrated circuit is implemented on a second semiconductor die that is separate from the first semiconductor die; the first integrated circuit comprises a plurality of capacitors constructed on the first semiconductor die that are coupled to a plurality of power supply grids on the second integrated circuit to serve as decoupling capacitance for logic circuits incorporated into the plurality of integrated circuits, including logic circuits incorporated into the second integrated circuit on the second semiconductor die, wherein the plurality of supply grids comprise a local switched power supply grid for power gating and a global unswitched power supply grid; and the first integrated circuit further comprises a plurality of power management units on the first semiconductor die and configured to provide a power supply to the first integrated circuit, wherein each power management unit of the plurality of power management units comprises: a voltage regulator configured to generate the voltage on the power supply, wherein the voltage regulator comprises one or more second capacitors formed using the DRAM fabrication process; and a register that is programmable with a magnitude of the voltage to be generated by the voltage regulator, and wherein the register is changeable during use to change the magnitude. ### Claim 17 (depends on 16) The system as recited in claim 16 wherein the integrated circuit package is a multi-chip module. ### Claim 18 (depends on 16) The system as recited in claim 16 wherein the integrated circuit package incorporates package-on-package technology. ### Claim 19 (depends on 16) The system as recited in claim 16 wherein the integrated circuit package incorporates chip-on-chip technology.