# US 10,311,937 B2 · Method and apparatus for precharge and refresh control > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,937 B2 - Document ID: US10311937B2 - Status: Granted - Kind: B2 - Application number: 16/175,684 - Filed: 2018-10-30 - Published: 2019-02-28 - Granted: 2019-06-04 - Earliest claimed: 2017-05-23 - Assignees: Micron Technology, Inc. - Applicants: Micron Technology, Inc. - Inventors: Michael Richter - Web page: https://patentgrep.com/patent/US10311937B2 ## CPC - G11C 11/40618: {Refresh operations over multiple banks or interleaving} - G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} - G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating - G11C 11/4094: Bit-line management or control circuits - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract Method and Apparatuses for transmitting and receiving commands for a semiconductor device are described. An example apparatus includes: a memory device including a plurality of banks, each bank including a plurality of memory cells; and a memory controller that transmits a first command and a plurality of address signals indicative of a memory cell in a first bank of the plurality of banks at a first time. The first command is indicative of performing a first memory operation, and a second memory operation different from the first memory operation. The memory device receives the first command and the plurality of address signals and further performs the second memory operation to the first bank responsive, at least a part, to the plurality, of address signals and the first command. ## Claims ### Claim 1 A method of receiving a command in a memory device, the method comprising: receiving a first command indicative of performing a first memory operation and a second memory operation for a first bank; decoding the first command; and performing the first memory operation and the second memory operation for the first bank. ### Claim 2 (depends on 1) The method of claim 1, wherein the first memory operation is a precharge operation and the second memory operation is a refresh operation. ### Claim 3 (depends on 2) The method of claim 2, further comprising: determining whether the first bank is in an active state after decoding the first command; and performing the first memory operation and the second memory operation for the first bank if the first bank is in an active state. ### Claim 4 (depends on 3) The method of claim 3, further comprising: disabling the first memory operation and performing the second memory operation for the first bank responsive to the first command, if the first bank is in an inactive state. ### Claim 5 (depends on 3) The method of claim 3, wherein the second memory operation comprises: counting a row access cycle time responsive to the first command; and activating the first bank during the row access cycle time. ### Claim 6 (depends on 5) The method of claim 5, wherein the first memory operation comprises: counting a precharge time responsive to the first command if the first bank is in an active state before counting the row access cycle time; and deactivating the first bank during the precharge time. ### Claim 7 (depends on 3) The method of claim 3, further comprising: receiving a second command following the first command; decoding the second command indicative of a third memory operation for a second bank different from the first bank; and performing the third memory operation for the second bank. ### Claim 8 (depends on 7) The method of claim 7, wherein the third memory operation is one command of a plurality of row access commands, the plurality of row access commands including a write command and a read command. ### Claim 9 A system comprising: a memory device including a first bank; and a memory controller configured to transmit at a time a first command and a plurality of address signals indicative of a memory cell in the first bank, wherein the first command is indicative of performing a first memory operation and performing a second memory operation different from the first memory operation, wherein the memory device is configured to receive the first command and to decode the first command, and further configured to perform either the first memory operation or the second memory operation different from the first memory operation for the first hank responsive to the first command. ### Claim 10 (depends on 9) The system of claim 9, wherein the memory device is further configured to determine whether the first bank is in an active state after decoding the first command, and to perform the first memory operation and the second memory operation for the first bank if the first hank is in the active state. ### Claim 11 (depends on 10) The system of claim 10, wherein the memory device is further configured to disable the first memory operation, and to perform the second memory operation for the first bank responsive to the first command, if the first bank is in an inactive state. ### Claim 12 (depends on 10) The system of claim 10, wherein the memory device is further configured to count a row access cycle time responsive to the first command, and to activate the first bank during the row access cycle time in the second memory operation. ### Claim 13 An apparatus comprising: a first bank; a command decoder configured to receive a first command and further configured to decode the first command; and a control logic circuit associated with the first bank, configured to perform either a first memory operation or a second memory operation different from the first memory operation for the first bank responsive to the first command. ### Claim 14 (depends on 13) The apparatus of claim 13, wherein the first memory operation is a precharge operation and the second memory operation is a refresh operation. ### Claim 15 (depends on 14) The apparatus of claim 14, wherein the control logic circuit is configured to determine whether the first bank is in an active state after decoding the first command, and to perform the first memory operation and the second memory operation for the first bank if the first bank is in the active state. ### Claim 16 (depends on 15) The apparatus of claim 15, wherein the control logic circuit is further configured to disable the first memory operation, and to perform the second memory operation for the first bank responsive to the first command, if the first bank is in an inactive state. ### Claim 17 (depends on 15) The apparatus of claim 15, wherein the control logic circuit is further configured to count a row access cycle time responsive to the first command, and to activate the first bank during the row access cycle time in the second memory operation. ### Claim 18 (depends on 17) The apparatus of claim 17, wherein the control logic circuit is further configured to count a precharge time responsive to the first command if the first bank is in the active state before counting the row access cycle time, and to deactivate the first bank during the precharge time in the first memory operation. ### Claim 19 (depends on 15) The apparatus of claim 15, wherein the command decoder is further configured to receive a second command following the first command, to decode the second command indicative of a third memory operation for a second bank different from the first bank, and wherein the control logic circuit is further configured to perform the third memory operation for the second bank. ### Claim 20 (depends on 19) The apparatus of claim 19, wherein the third memory operation is one command of a plurality of row access commands, the plurality of row access commands including a write command and a read command.