# US 10,311,936 B2 · Semiconductor memory device managing flexible refresh skip area > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,936 B2 - Document ID: US10311936B2 - Status: Granted - Kind: B2 - Application number: 15/233,942 - Filed: 2016-08-10 - Published: 2017-02-16 - Granted: 2019-06-04 - Earliest claimed: 2015-08-12 - Assignees: Samsung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Uksong Kang; Hoiju Chung - Web page: https://patentgrep.com/patent/US10311936B2 ## CPC - G11C 11/40615: {Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs} - G11C 11/406: Management or control of the refreshing or charge-regeneration cycles - G11C 11/40618: {Refresh operations over multiple banks or interleaving} - G11C 11/40622: {Partial refresh of memory arrays} - G11C 11/40626: {Temperature related aspects of refresh operations} - G11C 11/4087: {Address decoders, e.g. bit - or word line decoders; Multiple line decoders} - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A semiconductor memory device having a flexible refresh skip area includes a memory cell array including a plurality of rows to store data, a row decoder connected to the memory cell array, a refresh area storage unit to store a beginning address and an end address of a memory area that is to be refreshed in which the memory area that is to be refreshed does not include a refresh skip area having a size is selectively and/or adaptively changed, and a refresh control circuit connected to the row decoder and the refresh area storage unit. The refresh control circuit controls a refresh operation for the area that is to be refreshed and not for the refresh skip area. ## Claims ### Claim 1 A semiconductor memory device, comprising: a memory cell array including a plurality of rows to store data; a row decoder connected to the memory cell array; a refresh area storage unit to store a beginning address and an end address of a memory area of the memory cell array that is to be refreshed, the memory area that is to be refreshed not including a refresh skip area of the memory cell array having a size that is selectively changed; and a refresh control circuit connected to the row decoder, wherein the refresh control circuit controls a refresh operation for each row of the memory area that is to be refreshed and controls the refresh operation so that each row of the refresh skip area to not be refreshed. ### Claim 2 (depends on 1) The semiconductor memory device of claim 1, wherein the refresh control circuit controls the refresh operation so that the refresh operation is not received by the refresh skip area during the refresh operation. ### Claim 3 (depends on 2) The semiconductor memory device of claim 2, wherein the number of refresh commands generated for the memory area that is to be refreshed is based on a temperature of the semiconductor memory device. ### Claim 4 (depends on 1) The semiconductor memory device of claim 1, wherein the refresh control circuit controls a number of rows that are activated at the same time for the memory area that is to be refreshed is fewer than a number of rows that would be activated at the same time if there was no refresh skip area. ### Claim 5 (depends on 4) The semiconductor memory device of claim 4, wherein the number of rows that are activated is changed depending on a temperature of the semiconductor memory device. ### Claim 6 (depends on 1) The semiconductor memory device of claim 1, wherein the refresh control circuit controls an entire refresh operation period to be shorter than an entire refresh operation period if there was no refresh skip area. ### Claim 7 (depends on 6) The semiconductor memory device of claim 6, wherein a length of the entire refresh operation period is based on a temperature of the semiconductor memory device. ### Claim 8 (depends on 1) The semiconductor memory device of claim 1, wherein the refresh control circuit includes a refresh counter to count the refresh operation, and wherein a minimum counting value of the refresh counter is set to a counting value corresponding to the beginning address of the memory that is to be refreshed, and a maximum counting value of the refresh counter is set to a counting value corresponding to the ending address of the memory that is to be refreshed. ### Claim 9 (depends on 1) The semiconductor memory device of claim 1, wherein the refresh control circuit controls the refresh control operation differently depending on whether the semiconductor memory device is in an auto-refresh operation mode or a self-refresh operation mode. ### Claim 10 (depends on 1) The semiconductor memory device of claim 1, wherein the refresh area storage unit comprises a mode register. ### Claim 11 A semiconductor memory device, comprising: a memory cell array including a plurality of rows to store data; a row decoder connected to the memory cell array; a refresh area storage unit to store a beginning address and an end address of a memory area of the memory cell array that is to be refreshed, the memory area that is to be refreshed not including a refresh skip area of the memory cell array having a size that is selectively changed; and a refresh control circuit connected to the row decoder and the refresh area storage unit, wherein the refresh skip area includes at least one row among the plurality of rows of the memory cell array that is used as at least a part of a frame buffer to store data during a time period that is shorter than a time period for the refresh operation. ### Claim 12 (depends on 11) The semiconductor memory device of claim 11, wherein the refresh skip area further includes rows of the memory cell array that do not store data. ### Claim 13 (depends on 11) The semiconductor memory device of claim 11, wherein the refresh area storage unit comprises a mode register that stores mode register set signals. ### Claim 14 (depends on 11) The semiconductor memory device of claim 11, wherein the beginning address and the ending address that are stored in the refresh area storage unit are provided by a memory controller. ### Claim 15 (depends on 11) The semiconductor memory device of claim 11, wherein the refresh control circuit includes a refresh counter to count a refresh operation, wherein a minimum counting value of the refresh counter is set to a counting value corresponding to the beginning address of the memory area that is to be refreshed, and a maximum counting value of the refresh counter is set to a counting value corresponding to the ending address of the memory area that is to be refreshed, and wherein the refresh control circuit controls a refresh operation for each row of the memory area that is to be refreshed and controls the refresh operation of each row of the refresh skip area to not be refreshed. ### Claim 16 A semiconductor memory device, comprising: a memory cell array to store data; and a refresh control circuit coupled to the semiconductor memory device, the refresh control circuit to control a refresh operation of a memory area of the memory cell array that is to be refreshed, the memory area that is to be refreshed not including a refresh skip area of the memory cell array having a size that is selectively changeable based on data stored in the refresh skip area. ### Claim 17 (depends on 16) The semiconductor memory device of claim 16, wherein the data stored the refresh skip area comprises data for a frame buffer for a period of time that is less than a period of time of the refresh operation. ### Claim 18 (depends on 17) The semiconductor memory device of claim 17, wherein the refresh skip area contains no stored data. ### Claim 19 (depends on 16) The semiconductor memory device of claim 16, wherein the memory cell array comprises a plurality of rows to store the data, and wherein the refresh control circuit controls a refresh operation for each row of the memory area that is to be refreshed and controls the refresh operation for each row of the refresh skip area to not be refreshed. ### Claim 20 (depends on 19) The semiconductor memory device of claim 19, wherein the refresh control circuit further controls an interval of time between a refresh operation of each row of the memory area that is to be refreshed based on a temperature of the semiconductor device.