# US 10,311,935 B2 · Semiconductor device and method of driving the same

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- Number: US 10,311,935 B2
- Document ID: US10311935B2
- Status: Granted
- Kind: B2
- Application number: 15/907,484
- Filed: 2018-02-28
- Published: 2018-09-06
- Granted: 2019-06-04
- Earliest claimed: 2017-03-02
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Woo-Sung We; Hyun-Sung Lee
- Web page: https://patentgrep.com/patent/US10311935B2

## CPC

- G11C 11/406: Management or control of the refreshing or charge-regeneration cycles
- G11C 11/40611: {External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh}
- G11C 11/40618: {Refresh operations over multiple banks or interleaving}
- G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting
- G11C 11/408: Address circuits
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A semiconductor device according to an embodiment includes a plurality of memory regions suitable for performing a refresh operation based on a row address signal; an initialization circuit suitable for generating an initialization pulse signal for each refresh period during which a refresh pulse signal toggles as many times as the number of the memory regions; a control circuit suitable for activating a control pulse signal based on the refresh pulse signal and a plurality of memory address signals corresponding to the memory regions, and deactivating the control pulse signal based on the initialization pulse signal; and a row address generation circuit suitable for sequentially generating the row address signal based on the control pulse signal.

## Claims

### Claim 1

A semiconductor device, comprising:
a plurality of memory regions suitable for performing a refresh operation based on a row address signal;
an initialization circuit suitable for generating an initialization pulse signal for each refresh period during which a refresh pulse signal toggles as many times as the number of the memory regions;
a control circuit suitable for activating a control pulse signal based on the refresh pulse signal and a plurality of memory address signals corresponding to the memory regions, and deactivating the control pulse signal based on the initialization pulse signal; and
a row address generation circuit suitable for sequentially generating the row address signal based on the control pulse signal.

### Claim 2 (depends on 1)

The semiconductor device of claim 1, wherein the control circuit activates the control pulse signal when the memory address signals are normally generated for the each refresh period.

### Claim 3 (depends on 2)

The semiconductor device of claim 2, wherein the row address generation circuit changes the row address signal when the control pulse signal is activated.

### Claim 4 (depends on 1)

The semiconductor device of claim 1, wherein the control circuit maintains the control pulse signal in a deactivated state when at least one of the memory address signals is erroneously generated for the each refresh period.

### Claim 5 (depends on 4)

The semiconductor device of claim 4, wherein the row address generation circuit maintains the row address signal without change when the control pulse signal is deactivated.

### Claim 6 (depends on 1)

The semiconductor device of claim 1, wherein the initialization circuit counts a toggling number of the refresh pulse signal, and generates the initialization pulse signal when the toggling number of the refresh pulse signal reaches the number of the memory regions.

### Claim 7 (depends on 1)

The semiconductor device of claim 1, wherein the initialization circuit comprises:
at least one frequency division unit suitable for generating at least one refresh frequency division signal by dividing a frequency of the refresh pulse signal at a preset frequency division ratio; and
a first logic unit suitable for generating the initialization pulse signal by performing a logic operation on the refresh pulse signal and the refresh frequency division signal.

### Claim 8 (depends on 7)

The semiconductor device of claim 7, wherein the first logic unit performs a NAND operation on the refresh pulse signal and the refresh frequency division signal.

### Claim 9 (depends on 1)

The semiconductor device of claim 1, wherein the control circuit comprises:
a plurality of latch units suitable for latching the memory address signals based on the refresh pulse signal and suitable for being initialized based on the initialization pulse signal; and
a second logic unit suitable for generating the control pulse signal by performing a logic operation on a plurality of latch address signals latched in the latch units.

### Claim 10 (depends on 9)

The semiconductor device of claim 9, wherein the second logic unit performs an AND operation on the latch address signals.

### Claim 11

A method of driving a semiconductor device, comprising:
for each refresh period, sequentially generating a plurality of memory address signals corresponding to a plurality of memory regions and generating a refresh pulse signal that toggles as many times as the number of the memory regions;
for the each refresh period, activating an initialization pulse signal depending on a toggling number of the refresh pulse signal;
for the each refresh period, generating a control pulse signal based on the refresh pulse signal and the memory address signals, and initializing the control pulse signal based on the initialization pulse signal;
for the each refresh period, generating a row address signal based on the control pulse signal; and
for the each refresh period, performing a refresh operation for the memory regions based on the row address signal.

### Claim 12 (depends on 11)

The method of claim 11, wherein the initialization pulse signal is activated when the toggling number of the refresh pulse signal reaches the number of the memory regions.

### Claim 13 (depends on 11)

The method of claim 11, wherein the control pulse signal is activated when the memory address signals are normally generated.

### Claim 14 (depends on 13)

The method of claim 13, wherein the row address signal is changed when the control pulse signal is activated.

### Claim 15 (depends on 11)

The method of claim 11, wherein the control pulse signal is maintained in a deactivated state when at least one of the memory address signals is erroneously generated.

### Claim 16 (depends on 15)

The method of claim 15, wherein the row address signal is maintained without change when the control pulse signal is deactivated.

### Claim 17

A semiconductor device, comprising:
a plurality of memory regions suitable for performing a refresh operation for each refresh period, based on a plurality of memory address signals respectively corresponding to the memory regions, and a row address signal;
a control circuit suitable for activating a control pulse signal when the memory address signals are normally generated for the each refresh period; and
a row address generation circuit suitable for generating the row address signal while changing the row address signal when the control pulse signal is activated.

### Claim 18 (depends on 17)

The semiconductor device of claim 17, wherein the each refresh period includes a period during when a toggling number of a refresh pulse signal reaches the number of the memory regions, and
the control circuit deactivates the control pulse signal for a certain time before the each refresh period is ended.

### Claim 19 (depends on 18)

The semiconductor device of claim 18, wherein the control circuit maintains the control pulse signal in a deactivated state when at least one of the memory address signals is erroneously generated for the each refresh period.

### Claim 20 (depends on 19)

The semiconductor device of claim 19, wherein the row address generation circuit maintains the row address signal without a change when the control pulse signal is deactivated.