# US 10,311,931 B2 · Semiconductor memory device

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- Number: US 10,311,931 B2
- Document ID: US10311931B2
- Status: Granted
- Kind: B2
- Application number: 15/917,377
- Filed: 2018-03-09
- Published: 2019-03-21
- Granted: 2019-06-04
- Earliest claimed: 2017-09-20
- Assignees: Toshiba Memory Corporation
- Applicants: Toshiba Memory Corporation
- Inventors: Fumiyoshi Matsuoka; Kosuke Hatsuda
- Web page: https://patentgrep.com/patent/US10311931B2

## CPC

- G11C 11/1675: {Writing or programming circuits or methods}
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1657: {Word-line or row circuits}
- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 11/1693: {Timing circuits or methods}
- H10N 50/85: Materials of the active region
- H01F 10/3254: {the spacer being semiconducting or insulating, e.g. for spin tunnel junction [STJ]}
- H01F 10/3286: {Spin-exchange coupled multilayers having at least one layer with perpendicular magnetic anisotropy}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10N 50/10: Magnetoresistive devices
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H01F: MAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
- H10B: ELECTRONIC MEMORY DEVICES

## Abstract

According to one embodiment, a semiconductor memory device comprises a first memory cell including a first resistance change element; and a write circuit configured to write data to the first memory cell. The write circuit includes a first circuit including a first input terminal supplied with a first signal based on read data from the first memory cell and a second input terminal supplied with a second signal based on write data to the first memory cell; and a second circuit including a first input terminal supplied with a third signal from an output terminal of the first circuit and a second input terminal supplied with a fourth signal.

## Claims

### Claim 1

A semiconductor memory device comprising:
a first memory cell including a first resistance change element; and
a write circuit configured to perform write to the first memory cell,
wherein the write circuit includes:
a first circuit including a first input terminal supplied with a first signal based on read data from the first memory cell and a second input terminal supplied with a second signal based on write data to the first memory cell; and
a second circuit including a first input terminal supplied with a third signal from an output terminal of the first circuit and a second input terminal supplied with a fourth signal.

### Claim 2 (depends on 1)

The device of claim 1, wherein in the second circuit, the third signal as a set signal and the fourth signal as a reset signal are input signals.

### Claim 3 (depends on 1)

The device of claim 1, wherein:
the second circuit includes a latch circuit including a first NAND circuit and a second NAND circuit;
the first NAND circuit includes a first input terminal supplied with the third signal and a second input terminal coupled to an output terminal of the second NAND circuit; and
the second NAND circuit includes a first input terminal coupled to an output terminal of the first NAND circuit and a second input terminal supplied with the fourth signal.

### Claim 4 (depends on 1)

The device of claim 1, wherein the fourth signal is a signal based on a write command.

### Claim 5 (depends on 1)

The device of claim 1, wherein the first circuit outputs the third signal according to whether a logic level of the first signal and a logic level of the second signal are equal to each other.

### Claim 6 (depends on 1)

The device of claim 1, wherein the write circuit further includes a write driver configured to be driven based on a fifth signal from an output terminal of the second circuit.

### Claim 7 (depends on 6)

The device of claim 6, wherein after reading, the write circuit performs first write and performs second write after an interruption of the first write, and maintains the fifth signal at a first logic level to inhibit the write driver from being driven when the read data from the first memory cell, first write data in the first write, and second write data in the second write are equal.

### Claim 8 (depends on 6)

The device of claim 6, wherein after reading, the write circuit performs first write and performs second write after an interruption of the first write, and when the read data from the first memory cell and first write data in the first write are different, the write circuit maintains the fifth signal at a second logic level to drive the write driver in accordance with the first write data and drive the write driver in accordance with second write data until a transition of the fourth signal in the second write.

### Claim 9 (depends on 6)

The device of claim 6, wherein after reading, the write circuit performs first write and performs second write after an interruption of the first write, and when the read data from the first memory cell and first write data in the first write are equal, the write circuit maintains the fifth signal at a first logic level to inhibit the write driver from being driven, and when the read data from the first memory cell and second write data are different in the second write, the write circuit changes the fifth signal to a second logic level to drive the write driver in accordance with second write data.

### Claim 10 (depends on 3)

The device of claim 3, wherein the first NAND circuit further includes a third input terminal supplied with a sixth signal.

### Claim 11 (depends on 6)

The device of claim 6, wherein the write driver includes:
a first transistor including a first terminal coupled to a power supply voltage line and a control terminal supplied with a seventh signal based on the fifth signal and write data;
a second transistor including a first terminal coupled to the power supply voltage line and a control terminal supplied with an eighth signal based on the fifth signal and write data;
a third transistor including a first terminal coupled to a ground voltage line, a second terminal coupled to a second terminal of the first transistor, and a control terminal supplied with a ninth signal based on the fifth signal and write data; and
a fourth transistor including a first terminal coupled to the ground voltage line, a second terminal coupled to a second terminal of the first transistor, and a control terminal supplied with a tenth signal based on the fifth signal and write data.

### Claim 12

A semiconductor memory device comprising:
a first memory cell including a first resistance change element; and
a write circuit configured to write data to the first memory cell,
wherein after reading, the write circuit performs first write and performs second write after an interruption of the first write, and maintains a first signal at a first logic level when read data from the first memory cell, first write data in the first write, and second write data in the second write are all equal, and
wherein the write circuit further includes a write driver configured to be driven based on the first signal.

### Claim 13 (depends on 12)

The device of claim 12, wherein the write circuit includes:
a first circuit including a first input terminal supplied with a second signal based on read data from the first memory cell and a second input terminal supplied with a third signal based on write data to the first memory cell; and
a second circuit including a first input terminal supplied with a fourth signal from an output terminal of the first circuit and a second input terminal supplied with a fifth signal.

### Claim 14 (depends on 13)

The device of claim 13, wherein in the second circuit, the fourth signal as a set signal and the fifth signal as a reset signal are input signals.

### Claim 15 (depends on 13)

The device of claim 13, wherein:
the second circuit includes a latch circuit including a first NAND circuit and a second NAND circuit;
the first NAND circuit includes a first input terminal supplied with the fourth signal and a second input terminal coupled to an output terminal of the second NAND circuit; and
the second NAND circuit includes a first input terminal coupled to an output terminal of the first NAND circuit and a second input terminal supplied with the fifth signal.

### Claim 16 (depends on 13)

The device of claim 13, wherein the fifth signal is a signal based on a write command.

### Claim 17 (depends on 13)

The device of claim 13, wherein the first circuit outputs the fourth signal according to whether a logic level of the second signal and a logic level of the third signal are equal to each other.