# US 10,311,929 B2 · Resistance change memory

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- Number: US 10,311,929 B2
- Document ID: US10311929B2
- Status: Granted
- Kind: B2
- Application number: 15/835,988
- Filed: 2017-12-08
- Published: 2018-04-12
- Granted: 2019-06-04
- Earliest claimed: 2015-06-10
- Assignees: Toshiba Memory Corporation; SK hynix Inc.
- Applicants: Toshiba Memory Corporation; SK Hynix Inc.
- Inventors: Hisanori Aikawa; Tatsuya Kishi; Keisuke Nakatsuka; Satoshi Inaba; Masaru Toko; Keiji Hosotani; Jae Yun Yi; Hong Ju Suh; Se Dong Kim
- Web page: https://patentgrep.com/patent/US10311929B2

## CPC

- G11C 11/1673: {Reading or sensing circuits or methods}
- G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay}
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 8/12: Group selection circuits, e.g. for memory block selection, chip selection, array selection
- G11C 11/161: {details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell}
- G11C 11/1653: {Address circuits or decoders}
- G11C 11/1655: {Bit-line or column circuits}
- G11C 11/1657: {Word-line or row circuits}
- G11C 13/0023: {Address circuits or decoders}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- H10B 61/22: {of the field-effect transistor [FET] type}
- H10B 63/30: {comprising selection components having three or more electrodes, e.g. transistors}
- H10B 63/80: {Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}
- H10N 50/10: Magnetoresistive devices
- H10N 70/011: {Manufacture or treatment of multistable switching devices}
- H10N 70/063: {by etching of pre-deposited switching material layers, e.g. lithography}
- H10N 70/231: {based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect}
- H10N 70/826: {adapted for essentially vertical current flow, e.g. sandwich or pillar type devices}
- G11C 2213/79: Array wherein the access device being a transistor
- G11C 2213/82: Array having, for accessing a cell, a word line, a bit line and a plate or source line receiving different potentials
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H10B: ELECTRONIC MEMORY DEVICES
- H10N: ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR

## Abstract

According to an embodiment, a resistance change memory includes a semiconductor substrate, a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate, an insulating layer covering the transistor, a first conductive line connected to the first terminal and provided on the insulating layer, a second conductive line provided on the insulating layer, and a resistance change element connected between the second terminal and the second conductive line. The first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

## Claims

### Claim 1

A resistance change memory comprising:
a semiconductor substrate;
a transistor having a control terminal, a first terminal and a second terminal, the transistor provided on the semiconductor substrate;
an insulating layer covering the transistor;
a first conductive line connected to the first terminal and provided on the insulating layer;
a second conductive line provided on the insulating layer; and
a resistance change element connected between the second terminal and the second conductive line,
wherein the first conductive line has a width greater than a width of the second conductive line in a direction in which the first and second conductive lines are arranged.

### Claim 2 (depends on 1)

The memory of claim 1, further comprising:
a sense amplifier connected to the second conductive line.

### Claim 3 (depends on 2)

The memory of claim 2, further comprising:
a driver connecting the first conductive line to a ground terminal in a read operation using the sense amplifier.

### Claim 4 (depends on 3)

The memory of claim 3, further comprising:
a third conductive line above the first conductive line; and
a switch element having a first end and a second end, the first end connected to the first conductive line,
wherein the driver is connected between the second end of the switch element and the third conductive line.

### Claim 5 (depends on 3)

The memory of claim 3, further comprising:
a fourth conductive line above the second conductive line; and
a switch element connected between the second and fourth conductive lines.

### Claim 6 (depends on 1)

The memory of claim 1, wherein
the control terminal is provided in the semiconductor substrate.

### Claim 7 (depends on 1)

The memory of claim 1, wherein
the resistance change element comprises a first magnetic layer having invariable magnetization, a second magnetic layer having variable magnetization, and a nonmagnetic layer provided therebetween.