# US 10,311,926 B2 · Compensation of deterministic crosstalk in memory system > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,926 B2 - Document ID: US10311926B2 - Status: Granted - Kind: B2 - Application number: 15/851,957 - Filed: 2017-12-22 - Published: 2018-05-17 - Granted: 2019-06-04 - Earliest claimed: 2015-12-04 - Assignees: Integrated Device Technology, Inc. - Applicants: Integrated Device Technology, Inc. - Inventors: Craig DeSimone - Web page: https://patentgrep.com/patent/US10311926B2 ## CPC - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G11C 7/02: with means for avoiding parasitic signals - G11C 7/10: Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers - G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load} - G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory - G11C 11/4072: Circuits for initialization, powering up or down, clearing memory or presetting - G11C 11/4076: Timing circuits (for regeneration management G11C11/406) - G11C 11/4093: Input/output [I/O] data interface arrangements, e.g. data buffers - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract An apparatus includes a detector circuit and a receiver circuit. The detector circuit may be configured to generate a control signal indicating a start of a plurality of strobe edges in a strobe signal. The receiver circuit may be configured to initialize an equalizer circuit in response to the control signal. The equalizer circuit may be configured to compensate a data signal for crosstalk coupled from the strobe edges to the data signal. ## Claims ### Claim 1 An apparatus comprising: a detector circuit configured to generate a control signal indicating a start of a plurality of strobe edges in a strobe signal; and a receiver circuit configured to initialize an equalizer circuit in response to said control signal, wherein said equalizer circuit is configured to compensate a data signal for crosstalk coupled from said strobe edges to said data signal. ### Claim 2 (depends on 1) The apparatus according to claim 1, wherein said equalizer circuit is configured to adjust an amplitude of an output signal of said receiver circuit based on said strobe edges. ### Claim 3 (depends on 1) The apparatus according to claim 1, wherein said detector circuit and said receiver circuit form a data buffer circuit configured to couple a memory system to a backplane. ### Claim 4 (depends on 3) The apparatus according to claim 3, wherein said data buffer circuit is double data rate fourth generation (DDR4) compliant. ### Claim 5 (depends on 1) The apparatus according to claim 1, wherein said equalizer circuit comprises a counter circuit configured to generate a count signal that has a plurality of count edges that correspond to said strobe edges. ### Claim 6 (depends on 1) The apparatus according to claim 1, wherein (i) said equalizer circuit comprises a synchronization circuit configured to generate a synchronization signal that has a plurality of synchronization edges that correspond to a plurality of clock edges of a clock signal and (ii) said clock edges of said clock signal are aligned in time to said strobe edges. ### Claim 7 (depends on 1) The apparatus according to claim 1, wherein said equalizer circuit is configured to generate an intermediate signal having a plurality of intermediate edges timed with said crosstalk imposed on said data signal by said strobe signal. ### Claim 8 (depends on 7) The apparatus according to claim 7, wherein (i) said equalizer circuit further comprises a coefficient circuit configured to generate an equalization signal having a plurality of bursts in response to said intermediate edges and (ii) said bursts mimic said crosstalk. ### Claim 9 (depends on 8) The apparatus according to claim 8, wherein said equalizer circuit further comprises a summation circuit configured to cancel said crosstalk from said data signal by feedback of said bursts into said data signal. ### Claim 10 (depends on 1) The apparatus according to claim 1, wherein (i) said detector circuit and said receiver circuit are part of a dual in-line memory module (DIMM) and (ii) said DIMM is double data rate fourth generation (DDR4) compliant. ### Claim 11 A method for compensation of crosstalk in a memory system, comprising the steps of: generating a control signal indicating a start of a plurality of strobe edges in a strobe signal; initializing an equalizer circuit in response to said control signal; and compensating a data signal for said crosstalk coupled from said strobe signal to said data signal. ### Claim 12 (depends on 11) The method according to claim 11, further comprising the step of: adjusting an amplitude of an output signal based on corresponding edges of said strobe edges. ### Claim 13 (depends on 11) The method according to claim 11, wherein the steps are performed in a data buffer circuit configured to couple said memory system to a backplane. ### Claim 14 (depends on 13) The method according to claim 13, wherein said data buffer circuit is double data rate fourth generation (DDR4) compliant. ### Claim 15 (depends on 11) The method according to claim 11, further comprising the step of: generating a count signal that has a plurality of count edges that correspond to said strobe edges. ### Claim 16 (depends on 11) The method according to claim 11, further comprising the step of: generating a synchronization signal that has a plurality of synchronization edges that correspond to a plurality of clock edges of a clock signal, wherein said clock edges are aligned in time to said strobe edges. ### Claim 17 (depends on 11) The method according to claim 11, further comprising the step of: generating an intermediate signal having a plurality of intermediate edges timed with said crosstalk imposed on said data signal by said strobe signal. ### Claim 18 (depends on 17) The method according to claim 17, further comprising the steps of: generating an equalization signal having a plurality of bursts in response to said intermediate edges, wherein said bursts mimic said crosstalk; and cancelling said crosstalk from said data signal by feedback of said bursts into said data signal. ### Claim 19 (depends on 11) The method according to claim 11, wherein the steps are performed in a dual in-line memory module (DIMM). ### Claim 20 (depends on 19) The method according to claim 19, wherein said DIMM is double data rate fourth generation (DDR4) compliant.