# US 10,311,925 B2 · Apparatus and method for data clock calibration for a memory system with memory controller and memory devices > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,925 B2 - Document ID: US10311925B2 - Status: Granted - Kind: B2 - Application number: 15/832,127 - Filed: 2017-12-05 - Published: 2018-10-25 - Granted: 2019-06-04 - Earliest claimed: 2017-04-21 - Assignees: SK hynix Inc. - Applicants: SK hynix Inc. - Inventors: Young-Dong Roh - Web page: https://patentgrep.com/patent/US10311925B2 ## CPC - G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device} - G06F 3/0614: {Improving the reliability of storage systems} - G06F 3/0629: {Configuration or reconfiguration of storage systems} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G11C 7/062: {Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs} - G11C 8/06: Address interface arrangements, e.g. address buffers - G11C 8/18: Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals - G11C 29/023: {in clock generator or timing circuitry} - G11C 29/028: {with adaption or trimming of parameters} - G11C 29/36: Data generation devices, e.g. data inverters - G11C 29/52: Protection of memory contents; Detection of errors in memory contents - G11C 7/1072: {for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories} - G11C 2207/2254: Calibration - G11C: STATIC STORES (semiconductor memory devices H10B) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A memory system may include: a controller suitable for: generating a first clock and first pattern data having a first phase difference, in a write calibration mode, calibrating, the first phase difference depending on a second information, in a read calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, a first information according to comparing of the first and second values, receiving by calibrating, a second phase difference generated by a memory device depending on the first information; and the memory device suitable for: generating the second clock and the second pattern data having the second phase difference, in the write calibration mode, detecting, a first and second value of the first and second pattern data according to the first and second clock, generating, the second information according to comparing of the first and second values. ## Claims ### Claim 1 A memory system comprising: a controller configured to: generate a first data clock and first pattern data having a first phase difference, calibrate, in a write calibration mode, the first phase difference depending on a second comparison information, detect, in a read calibration mode, a first value of the first pattern data according to the first data clock and a second value of a second pattern data according to a second data clock, compare, in the read calibration mode, the first and second values detected in the read calibration mode, generate, in the read calibration mode, a first comparison information according to a result of the comparing of the first and second values detected in the read calibration mode, and calibrate, in the read calibration mode, a second phase difference generated by a memory device depending on the first comparison information; and the memory device configured to: generate the second data clock and the second pattern data having the second phase difference, detect, in the write calibration mode, the first value of the first pattern data according to the first data clock and the second value of the second pattern data according to the second data clock, compare, in the write calibration mode, the first and second values detected in the write calibration mode, and generate, in the write calibration mode, the second comparison information according to a result of the comparing of the first and second values detected in the write calibration mode, wherein the controller further comprises a calibration command generation unit configured to control activation of the read calibration mode and the write calibration mode by generating a read calibration command and a write calibration command, respectively, and wherein the calibration command generation unit generates the read calibration command in response to a read calibration period entered at a first predetermined time point during a booting operation period and then selects whether to additionally generate the read calibration command, in response to the output signal of the first comparison unit, and generates the write calibration command in response to a write calibration period entered at a second predetermined time point and then selects whether to additionally generate the write calibration command, in response to the comparison information. ### Claim 2 (depends on 1) The memory system according to claim 1, wherein the controller comprises: a first generation unit configured to: generate the first data clock and the first pattern data, and calibrate, in the write calibration mode, the first phase difference depending on the second comparison information; a first comparison unit configured to: detect, in the read calibration mode, the first and second values, compare, in the read calibration mode, the first and second values detected in the read calibration mode, and generate, in the read calibration mode, the first comparison information; and a first calibration unit configured to calibrate, in the read calibration mode, the second phase difference. ### Claim 3 (depends on 1) The memory system according to claim 1, wherein the memory device comprises: a second generation unit configured to generate the second data clock and the second pattern data; and a second comparison unit configured to: detect, in the write calibration mode, the first and second values, compare, in the write calibration mode, the first and second values detected in the write calibration mode, and generate, in the write calibration mode, the second comparison information. ### Claim 4 (depends on 1) The memory system according to claim 1, wherein the first pattern data generated by the controller is the same as the second pattern data generated by the memory device. ### Claim 5 (depends on 1) The memory system according to claim 1, wherein the controller further comprises a determination unit configured to control the calibration command generation unit to generate the read and write calibration commands based on a number of bit flips of normal data read from the memory device in a normal operation period. ### Claim 6 (depends on 5) The memory system according to claim 5, wherein the calibration command generation unit generates the read calibration command and the write calibration command in response to an intermediate calibration period selected in terms of whether to enter, depending on an output signal of the determination unit, is entered during the normal operation period, and then selects whether to generate additionally the read calibration command, in response to the output signal of the first comparison unit, and selects whether to generate additionally the write calibration command, in response to the comparison information. ### Claim 7 (depends on 6) The memory system according to claim 6, wherein the determination unit checks whether an idle state of the memory device is retained for at least a predetermined time during the normal operation period, and selects whether the calibration command generation unit will enter the intermediate calibration period, depending on a checking result. ### Claim 8 A memory system comprising: a controller configured to: in a first write calibration mode, generate and output a first data clock and first pattern data which are calibrated in a phase difference thereof depending on a first comparison information inputted thereto; in a second write calibration mode, generate and output a second data clock and second pattern data which are calibrated in a phase difference thereof depending on a second comparison information inputted thereto; in a first read calibration mode, determine a value of third pattern data inputted thereto based on a third data clock inputted thereto and receive the third data clock having a phase calibrated depending on a result of comparing the value of the third pattern data with a value of the first pattern data generated therein; and, in a second read calibration mode, determine a value of fourth pattern data inputted thereto based on a fourth data clock inputted thereto and receive the fourth data clock having a phase calibrated depending on a result of comparing the value of the fourth pattern data with a value of the second pattern data generated therein; a first memory device configured to: in the first write calibration mode, determine the value of the first pattern data inputted thereto based on the first data clock inputted thereto and generate and output the first comparison information of which value is determined depending on a result of comparing the value of the first pattern data with the value of the third pattern data generated therein, and, in the first read calibration mode, generate and output the third pattern data and the third data clock which have a predetermined phase difference; and a second memory device configured to: in the second write calibration mode, determine the value of the second pattern data inputted thereto based on the second data clock inputted thereto and generate and output the second comparison information of which value is determined depending on a result of comparing the value of the second pattern data with the value of the fourth pattern data generated therein, and, in the second read calibration mode, generate and output the fourth pattern data and the fourth data clock which have a predetermined phase difference, wherein the controller further comprises: a first generation unit configured to: in the first read calibration mode, generate the first pattern data and the first data clock which have the predetermined phase difference; in the second read calibration mode, generate the second pattern data and the second data clock which have the predetermined phase difference; in the first write calibration mode, generate the first data clock and the first pattern data which are calibrated in the phase difference thereof depending on the first comparison information; and in the second write calibration mode, generate the second data clock and the second pattern data which are calibrated in the phase difference thereof depending on the second comparison information; a first comparison unit configured to, in the first read calibration mode, compare the value of the first pattern data determined based on the first data clock and the value of the third pattern data determined based on the third data clock inputted from the first memory device; a second comparison unit configured to, in the second read calibration mode, compare the value of the second pattern data determined based on the second data clock and the value of the fourth pattern data determined based on the fourth data clock inputted from the second memory device; a first calibration unit configured to, in the first read calibration mode, receive the third data clock having the phase calibrated in response to an output signal of the first comparison unit so that a phase difference of the third data clock and the third pattern data are calibrated; and second calibration unit configured to, in the second read calibration mode, receive the fourth data clock having the phase calibrated in response to an output signal of the second comparison unit so that a phase difference of the fourth data clock and the fourth pattern data are calibrated. ### Claim 9 (depends on 8) The memory system according to claim 8, wherein the first memory device comprises: a second generation unit configured to, in the first read calibration mode and the first write calibration mode, generate the third pattern data and the third data clock which have the predetermined phase difference; and a third comparison unit configured to, in the first write calibration mode, compare the value of the third pattern data determined based on the third data clock and the value of the first pattern data determined based on the first data clock inputted from the controller and determine and generate the value of the first comparison information depending on a comparison result. ### Claim 10 (depends on 9) The memory system according to claim 9, wherein the second memory device comprises: a third generation unit configured to, in the second read calibration mode and the second write calibration mode, generate the fourth pattern data and the fourth data clock which have the predetermined phase difference; and a fourth comparison unit configured to, in the second write calibration mode, compare the value of the fourth pattern data determined based on the fourth data clock and the value of the second pattern data determined based on the second data clock inputted from the controller and determine and generate the value of the second comparison information depending on a comparison result. ### Claim 11 (depends on 10) The memory system according to claim 10, wherein the value of the first pattern data determined based on the first data clock generated in the first generation unit of the controller and the value of the third pattern data determined based on the third data clock generated in the second generation unit of the first memory device are the same with each other, and wherein the value of the second pattern data determined based on the second data clock generated in the first generation unit of the controller and the value of the fourth pattern data determined based on the fourth data clock generated in the third generation unit of the second memory device are the same with each other. ### Claim 12 (depends on 11) The memory system according to claim 11, wherein the controller further comprises: a calibration command generation unit configured to generate a first read calibration command for controlling entry to the first read calibration mode, generate a second read calibration command for controlling entry to the second read calibration mode, generate a first write calibration command for controlling entry to the first write calibration mode, and generate a second write calibration command for controlling entry to the second write calibration mode. ### Claim 13 (depends on 12) The memory system according to claim 12, wherein the calibration command generation unit generates the first and second read calibration commands in response to that a read calibration period is entered at a first predetermined time point during a booting operation period, and then selects whether to additionally generate the first read calibration command, in response to the output signal of the first comparison unit, and selects whether to additionally generate the second read calibration command, in response to the output signal of the second comparison unit, and wherein the calibration command generation unit generates the first and second write calibration commands in response to that a write calibration period is entered at a second predetermined time point, and then selects whether to additionally generate the first write calibration command, in response to the first comparison information, and selects whether to additionally generate the second write calibration command, in response to the second comparison information. ### Claim 14 (depends on 12) The memory system according to claim 12, wherein the controller further comprises: a first determination unit configured to determine whether the number of bit flips of data inputted from the first memory device in a normal operation period exceeds a predetermined reference; and a second determination unit configured to determine whether the number of bit flips of data inputted from the second memory device in the normal operation period exceeds the predetermined reference. ### Claim 15 (depends on 14) The memory system according to claim 14, wherein the calibration command generation unit generates the first read calibration command and the first write calibration command in response to that a first intermediate calibration period selected in terms of whether to enter, depending on an output signal of the first determination unit, is entered during the normal operation period, and then selects whether to generate additionally the first read calibration command, in response to the output signal of the first comparison unit, and selects whether to generate additionally the first write calibration command, in response to the first comparison information, and wherein the calibration command generation unit generates the second read calibration command and the second write calibration command in response to that a second intermediate calibration period selected in terms of whether to enter, depending on an output signal of the second determination unit, is entered during the normal operation period, and then selects whether to generate additionally the second read calibration command, in response to the output signal of the second comparison unit, and selects whether to generate additionally the second write calibration command, in response to the second comparison information. ### Claim 16 (depends on 15) The memory system according to claim 15, wherein the first determination unit checks whether an idle state of the first memory device is retained for at least a predetermined time during the normal operation period, and selects whether the calibration command generation unit will enter the first intermediate calibration period, depending on a checking result, and wherein the second determination unit checks whether an idle state of the second memory device is retained for at least the predetermined time during the normal operation period, and selects whether the calibration command generation unit will enter the second intermediate calibration period, depending on a checking result.