# US 10,311,923 B2 · Input circuit of three-dimensional semiconductor apparatus capable of enabling testing and direct access

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- Number: US 10,311,923 B2
- Document ID: US10311923B2
- Status: Granted
- Kind: B2
- Application number: 15/416,130
- Filed: 2017-01-26
- Published: 2017-05-11
- Granted: 2019-06-04
- Earliest claimed: 2014-12-05
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Dae Suk Kim
- Web page: https://patentgrep.com/patent/US10311923B2

## CPC

- G11C 7/22: Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C 7/1078: {Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits}
- G11C 29/1201: {comprising I/O circuitry}
- H03K 5/22: Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral (indicating phase difference of two cyclic pulse trains G01R25/00)
- G11C 5/04: Supports for storage elements {, e.g. memory modules}; Mounting or fixing of storage elements on such supports
- G11C 7/1084: {Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load}
- H10W 70/63: Vias, e.g. via plugs
- H10W 90/722: {between stacked chips}
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H03K: PULSE TECHNIQUE (measuring pulse characteristics G01R; modulating sinusoidal oscillations with pulses H03C; transmission of digital information H04L; discriminator circuits detecting phase difference between two signals by counting or integrating cycles of oscillation H03D3/04; automatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses where the type of generator is irrelevant or unspecified H03L; coding, decoding or code conversion, in general H03M)
- H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10

## Abstract

An input circuit of a semiconductor apparatus may include a first input buffer configured to receive a signal through a test input terminal and to output a first input signal, a second input buffer configured to receive a signal through a normal input terminal and to output a second input signal. The input circuit of the semiconductor apparatus may include a switching unit configured to transfer the signal inputted through the test input terminal to the second input buffer according to a test mode signal. The input circuit of the semiconductor apparatus may include a comparison unit configured to compare the first input signal with the second input signal and to generate a comparison signal, and a storage unit configured to store the comparison signal.

## Claims

### Claim 1

An input circuit of a semiconductor apparatus, comprising:
a first input buffer configured to receive a first signal through a test input terminal and to output a first input signal;
a second input buffer configured to receive a second signal through a normal input terminal and to output a second input signal;
a switching unit configured to transfer the first signal inputted through the test input terminal to the second input buffer according to a test mode signal;
a comparison unit configured to compare the first input signal with the second input signal and to generate a comparison signal; and
a storage unit configured to store the comparison signal,
wherein, the semiconductor apparatus includes a semiconductor memory module and a memory controller, and
wherein the test input terminal includes a direct access ball (DAB) exposed to an exterior of the semiconductor apparatus to access the memory module directly,
wherein a direct access mode circuit is configured to perform an operation related to a direct access mode according to the first input signal, and
wherein a data, inputted from a test equipment through the DAB in order to directly test the memory module, is transferred to the direct access mode circuit through the first input buffer, so that a memory module test operation is performed by the direct access mode circuit.

### Claim 2 (depends on 1)

The input circuit of a semiconductor apparatus according to claim 1, wherein the normal input terminal includes a micro bump located within the semiconductor apparatus.

### Claim 3 (depends on 1)

The input circuit of a semiconductor apparatus according to claim 1, further comprising:
a normal mode circuit configured to perform an operation including data write or read related to a normal mode according to the second input signal.

### Claim 4 (depends on 1)

The input circuit of a semiconductor apparatus according to claim 1, wherein the comparison unit is configured to perform a XNOR logic.

### Claim 5 (depends on 1)

The input circuit of a semiconductor apparatus according to claim 1, wherein the comparison unit compares the first input signal with the second input signal and to generate the comparison signal according to a clock signal.

### Claim 6 (depends on 1)

The input circuit of a semiconductor apparatus according to claim 1, wherein the storage unit includes a register accessible from an exterior of the semiconductor apparatus.