# US 10,311,922 B2 · Shifting data

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- Number: US 10,311,922 B2
- Document ID: US10311922B2
- Status: Granted
- Kind: B2
- Application number: 16/006,514
- Filed: 2018-06-12
- Published: 2018-10-11
- Granted: 2019-06-04
- Earliest claimed: 2016-06-03
- Assignees: Micron Technology, Inc.
- Applicants: Micron Technology, Inc.
- Inventors: Glen E. Hush
- Web page: https://patentgrep.com/patent/US10311922B2

## CPC

- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/065: {Differential amplifiers of latching type}
- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G11C 7/1012: {Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating}
- G11C 7/222: {Clock generating, synchronizing or distributing circuits within memory device}
- G11C 8/04: using a sequential addressing device, e.g. shift register, counter
- G11C 11/4076: Timing circuits (for regeneration management G11C11/406)
- G11C 11/4094: Bit-line management or control circuits
- G11C 11/4096: Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
- G11C 11/4091: Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

The present disclosure includes apparatuses and methods related to shifting data. A number of embodiments of the present disclosure include an apparatus comprising a shift register comprising an initial stage and a final stage. The shift register may be configured such that a clock signal may be initiated at the final stage of the shift register.

## Claims

### Claim 1

An apparatus, comprising:
a shift register comprising:
an initial stage corresponding to a first storage location of the shift register and located at a first end of the shift register; and
a final stage corresponding to a final storage location of the shift register and located at a second end of the shift register, the first end of the shift register and the second end of the shift register being disposed at opposite ends of the shift register, wherein the shift register is configured to send a data value stored in the final stage directly to the initial stage.

### Claim 2 (depends on 1)

The apparatus of claim 1, further comprising a clock driver to generate the clock signal, wherein the clock driver is disposed at the second end of the shift register.

### Claim 3 (depends on 1)

The apparatus of claim 1, comprising
an array of memory cells coupled to sensing circuitry including the shift register; and
a clock driver coupled to the array, the clock driver to:
generate a clock signal; and
control timing of shifting data stored in the sensing circuitry based, at least in part, on the clock signal.

### Claim 4 (depends on 3)

The apparatus of claim 3, further comprising second sensing circuitry coupled to the sensing circuitry, the second sensing circuitry configured to receive data from an output of the sensing circuitry.

### Claim 5 (depends on 1)

The apparatus of claim 1, wherein the shift register is configured to send the data value stored in the final stage to the initial stage without altering a frequency of a clock signal provided to the shift register.

### Claim 6 (depends on 1)

The apparatus of claim 1, further comprising:
a number of repeater devices disposed along a data path; and
a number of repeater devices disposed along a clock signal path, wherein the number of repeater devices disposed along the data path is equal to the number of repeater devices disposed along the clock signal path.

### Claim 7 (depends on 1)

The apparatus of claim 1, wherein the shift register is configured to send the data value stored in the final stage directly to the initial stage without accessing a processing resource associated with a host coupled to the shift register.

### Claim 8

A system, comprising:
an array of memory cells;
sensing circuitry coupled to the array and comprising a shift register; and
a controller configured to:
cause data stored in the shift register to be shifted from an initial stage corresponding to a first storage location of the shift register to a second stage;
cause data stored in the second stage to be shifted to a final stage corresponding to a final storage location of the shift register, wherein the initial stage and the final stage are located at opposite ends of the shift register; and
cause data stored in the final stage to be shifted directly to the initial stage, wherein the initial stage is at a first end of the shift register and the final stage is at a second end of the shift register.

### Claim 9 (depends on 8)

The system of claim 8, wherein the system includes:
a memory device comprising the sensing circuitry and the controller; and
a host coupled to the memory device, wherein the controller is further configured to cause the data to be shifted without transferring data from the memory device to the host.

### Claim 10 (depends on 8)

The system of claim 8, wherein the shift register includes greater than 100 stages.

### Claim 11 (depends on 8)

The system of claim 8, wherein the controller is configured to cause a clock signal to be received at a stage of the shift register different from an initial stage of the shift register.

### Claim 12 (depends on 8)

The system of claim 8, wherein the shift register comprises a compute component that comprises transistors formed on pitch with memory cells of the array.

### Claim 13 (depends on 8)

The system of claim 8, further comprising a clock driver coupled to the shift register, wherein the controller is configured to cause the clock driver to generate at least one clock phase that propagates in a direction different than a direction that the data value is shifted.

### Claim 14

A method, comprising:
shifting data stored in a shift register according to a clock signal; and
performing a rotate operation to shift the data directly from an initial stage corresponding to a first storage location of the shift register and located at a first end of the shift register to a final stage corresponding to a final storage location of the shift register and located at a second end of the shift register, wherein the first end of the shift register and the second end of the shift register are at opposite ends of the shift register.

### Claim 15 (depends on 14)

The method of claim 14, wherein shifting data comprises shifting data stored in a first stage to a second stage during a clock cycle associated with the clock signal.

### Claim 16 (depends on 14)

The method of claim 14, wherein the method includes generating a clock signal at a stage of the shift register different than an input stage of the shift register.

### Claim 17 (depends on 14)

The method of claim 14, wherein the method includes generating a clock signal at a final output stage of the shift register.

### Claim 18 (depends on 14)

The method of claim 14, wherein shifting the data includes shifting the data contrariwise to a direction of propagation of a clock signal applied to the shift register.

### Claim 19 (depends on 14)

The method of claim 14, wherein the method includes shifting data associated with the shift register from a final output stage of the shift register to an initial input stage of the shift register without altering a frequency associated with a clock signal applied to the shift register.

### Claim 20 (depends on 14)

The method of claim 14, wherein performing the rotate operation further comprises performing the rotate operation without transferring the data to circuitry external to the shift register.