# US 10,311,921 B1 · Multiple-mode current sources for sense operations

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- Number: US 10,311,921 B1
- Document ID: US10311921B1
- Status: Granted
- Kind: B1
- Application number: 15/858,535
- Filed: 2017-12-29
- Granted: 2019-06-04
- Earliest claimed: 2017-12-29
- Assignees: SanDisk Technologies LLC
- Applicants: SanDisk Technologies LLC
- Inventors: Ward Parkinson; Thomas Michael Trent; James Edwin O'Toole
- Web page: https://patentgrep.com/patent/US10311921B1

## CPC

- G11C 7/12: Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 8/08: Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
- G11C 13/0004: {comprising amorphous/crystalline phase transition cells}
- G11C 13/004: {Reading or sensing circuits or methods}
- G11C 13/0026: {Bit-line or column circuits}
- G11C 13/0028: {Word-line or row circuits}
- G11C 2213/76: Array using an access device for each cell which being not a transistor and not a diode
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A bit line read voltage generator may operate in a high drive strength or current mode to drive a selected bit line voltage to a read selected bit line voltage at a high level, and then may switch to operating in a low drive strength or current mode. Doing so may control, such as by limiting, the amount of cell current if the selected memory cell turns on, reducing the likelihood of false writes. Also, a word line read voltage generator may operate in a high drive strength or current mode to ramp up a selected word line voltage level, and then may switch to operating in a low drive strength or current mode to shorten the time for a global selected word line voltage to decrease to below a trip level and/or to control an amount of the cell current when the selected memory cell turns on.

## Claims

### Claim 1

A circuit comprising:
a memory array comprising a plurality of memory cells;
a sense circuit configured to:
sense a global selected word line voltage of a selected word line; and
output a sense result signal indicative of a logic level of data stored in a selected memory cell coupled to the selected word line; and
a voltage generator configured to:
set a global selected bit line voltage to a selected bit line voltage level according to a drive strength at an initial drive strength level;
decrease the drive strength of the voltage supply from the initial drive strength level to a decreased drive strength level in response to the global selected bit line voltage set to the selected bit line voltage level; and
in response to the selected memory cell of the plurality of memory cells turning on, control a memory cell current through the selected memory cell according to the decreased drive strength level.

### Claim 2 (depends on 1)

The circuit of claim 1, wherein the voltage generator comprises:
a first current branch configured to set the global selected bit line voltage according to the drive strength at the initial drive strength level; and
a second current branch configured to set the global selected bit line voltage according to the drive strength at the decreased drive strength level.

### Claim 3 (depends on 2)

The circuit of claim 2, further comprising a controller configured to:
activate the first current branch to set the global selected bit line voltage according to the drive strength at the initial drive strength level; and
deactivate the first current branch to set the global selected bit line voltage according to the drive strength at the decreased drive strength level.

### Claim 4 (depends on 3)

The circuit of claim 3, wherein the voltage generator is configured to:
decrease the global selected bit line voltage from an unselected bit line voltage level to the selected bit line voltage level according to the drive strength at the initial drive strength level during an initial portion of a bit line set period of a sense operation; and
maintain the global selected bit line voltage at the selected bit line voltage level during a remaining portion of the bit line set period and a word line set period.

### Claim 5 (depends on 2)

The circuit of claim 2, wherein the first current branch is configured to draw a first branch current at a first branch current level, and
wherein the second branch current is configured to draw a second branch current at a second branch current level that is lower than the first branch current level.

### Claim 6 (depends on 1)

The circuit of claim 1, wherein the selected memory cell is configured to turn on during a sense operation when programmed in a low resistance state, and when turned on, is configured to conduct a spiked portion and a decaying portion of the memory cell current during a memory cell response period, and wherein the voltage generator is configured to conduct a global bit line current according to the drive strength at the decreased drive strength level during the memory cell response period.

### Claim 7 (depends on 1)

The circuit of claim 1, wherein the voltage generator is configured to sink a global bit line current from a global selected bit line node according to the drive strength at the decreased drive strength level in order to control the memory cell current.

### Claim 8

A circuit comprising:
a memory array comprising a plurality of memory cells;
means for setting a global selected bit line voltage to a selected bit line voltage level according to a drive strength at an initial drive strength level;
means for decreasing the drive strength of the voltage supply from the initial drive strength level to a decreased drive strength level in response to the global selected bit line select voltage set to the selected bit line voltage level; and
means for controlling a memory cell current through the selected memory cell according to the decreased drive strength level in response to the selected memory cell turning on.

### Claim 9 (depends on 8)

The circuit of claim 8, further comprising:
means for setting the global selected bit line voltage according to the drive strength at the initial drive strength level; and
means for setting the global selected bit line voltage according to the drive strength at the decreased drive strength level.

### Claim 10 (depends on 9)

The circuit of claim 9, further comprising:
means for activating the first current branch to set the global selected bit line voltage according to the drive strength at the initial drive strength level; and
means for deactivating the first current branch to set the global selected bit line voltage according to the drive strength at the decreased drive strength level.

### Claim 11 (depends on 10)

The circuit of claim 10, further comprising:
means for decreasing the global selected bit line voltage from an unselected bit line voltage level to the selected bit line voltage level according to the drive strength at the initial drive strength level during an initial portion of a bit line set period of a sense operation; and
means for maintaining the global selected bit line voltage at the selected bit line voltage level during a remaining portion of the bit line set period and a word line set period.

### Claim 12 (depends on 9)

The circuit of claim 9, wherein the means for setting the global selected bit line voltage comprises a means for drawing a first branch current at a first branch current level, and
wherein the means for setting the global selected bit line voltage comprises a means for drawing a second branch current at a second branch current that is lower than the first branch current level.

### Claim 13 (depends on 8)

The circuit of claim 8, wherein the selected memory cell is configured to turn on during a sense operation when programmed in a low resistance state, and when turned on, is configured to conduct a spiked portion and a decaying portion of the memory cell current during a memory cell response period, the circuit further comprising means for conducting a global bit line current according to the drive strength at the reduced drive strength level during the memory cell response period.

### Claim 14 (depends on 8)

The circuit of claim 8, further comprising means for sinking a global bit line current from a global selected bit line node according to the drive strength at the reduced drive strength level in order to control the memory cell current.

### Claim 15

A method comprising:
outputting, with a sense circuit, a sense result signal indicative of a logic level of data stored in a selected memory cell of a memory array coupled to a selected word line;
setting, with a voltage generator, a global selected bit line voltage to a selected bit line voltage level according to a drive strength at an initial drive strength level;
decreasing, with the voltage generator, the drive strength of the voltage supply from the initial drive strength level to a decreased drive strength level in response to the global selected bit line voltage set to the selected bit line voltage level; and
in response to the selected memory cell of the plurality of memory cells turning on, controlling, with the voltage generator, a memory cell current through the selected memory cell according to the decreased drive strength level.

### Claim 16 (depends on 15)

The method of claim 15, further comprising:
activating, with a controller, a current branch to set the global selected bit line voltage according to the drive strength at the initial drive strength level; and
deactivating, with the controller, the current branch to set the global selected bit line voltage according to the drive strength at the decreased drive strength level.

### Claim 17 (depends on 16)

The method of claim 16, further comprising:
decreasing, with the voltage generator, the global selected bit line voltage from an unselected bit line voltage level to the selected bit line voltage level according to the drive strength at the initial drive strength level during an initial portion of a bit line set period of a sense operation; and
maintaining, with the voltage generator, the global selected bit line voltage at the selected bit line voltage level during a remaining portion of the bit line set period and a word line set period.

### Claim 18 (depends on 15)

The method of claim 15, further comprising:
drawing, with a first current branch of the voltage generator, a first branch current at a first branch current level to set the global selected bit line voltage to the selected bit line voltage level according to the drive strength at the initial drive strength level; and
drawing, with a second current branch of the voltage generator, a second branch current at a second branch current level that is lower than the first branch current level to set the global selected bit line voltage according to the drive strength at the decreased drive strength level.

### Claim 19 (depends on 15)

The method of claim 15, further comprising:
turning on the selected memory cell during a sense operation when programmed in a low resistance state;
conducting, with the selected memory cell, a spiked portion and a decaying portion of the memory cell current during a memory cell response period; and
conducting, with the voltage generator, a global bit line current according to the drive strength at the decreased drive strength level during the memory cell response period.

### Claim 20 (depends on 15)

The method of claim 15, further comprising:
sinking, with the voltage generator, a global bit line current from a global selected bit line node according to the drive strength at the decreased drive strength level in order to control the memory cell current.