# US 10,311,920 B2 · Apparatus and method for controlling memory device

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- Number: US 10,311,920 B2
- Document ID: US10311920B2
- Status: Granted
- Kind: B2
- Application number: 15/651,084
- Filed: 2017-07-17
- Published: 2018-06-07
- Granted: 2019-06-04
- Earliest claimed: 2016-12-05
- Assignees: SK hynix Inc.
- Applicants: SK hynix Inc.
- Inventors: Tae-Kyu Ryu
- Web page: https://patentgrep.com/patent/US10311920B2

## CPC

- G11C 7/1006: {Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor}
- G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors}
- G06F 3/064: {Management of blocks}
- G06F 11/08: Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F 11/1048: {using arrangements adapted for a specific error detection or correction feature}
- G11C 7/14: Dummy cell management; Sense reference voltage generators
- G11C 11/5642: {Sensing or reading circuits; Data output circuits}
- G11C 16/0483: {comprising cells having several storage transistors connected in series}
- G11C 29/021: {in voltage or current generators}
- G11C 29/028: {with adaption or trimming of parameters}
- G11C 29/42: using error correcting codes [ECC] or parity check
- G11C 29/50: Marginal testing, e.g. race, voltage or current testing
- G11C 29/52: Protection of memory contents; Detection of errors in memory contents
- G11C 16/26: Sensing or reading circuits; Data output circuits
- G11C 29/50004: {of threshold voltage}
- G11C 2029/0409: {Online test}
- G11C 2029/0411: {Online error correction}
- G11C 2211/5634: Reference cells
- G11C: STATIC STORES (semiconductor memory devices H10B)
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

An apparatus for controlling a memory device may include: a table storing information of a plurality of read voltages; an error correction unit suitable for correcting an error of read data; and a processor functionally coupled to the RR table and the error correction unit. The processor selects a default read voltage among the plurality of read voltages from the table when a read fail for the memory device is recognized, sets a shift direction of the default read voltage based on the number of read cells of the memory device read by the default read voltage, and controls a read retry operation of the memory device based on at least one read voltage in the set shift direction in the table.

## Claims

### Claim 1

An apparatus for controlling a memory device, comprising:
a table storing information of a plurality of read voltages;
a voltage supply generating the plurality of read voltages;
an error correction unit correcting an error of read data; and
a processor functionally coupled to the table and the error correction unit to perform a read retry operation,
wherein the processor is configured to select a default read voltage among the plurality of read voltages from the table when a read fail for the memory device is recognized, use the default read voltage to read cells of the memory device, set a shift direction of the default read voltage based on a count of read cells for determining a next read voltage in the table, and use the next read voltage to read the cells of the memory device for the read retry operation.

### Claim 2 (depends on 1)

The apparatus of claim 1, wherein the processor sets the shift direction of the default read voltage to a positive direction when the number of read cells is smaller than a reference cell number, and sets the shift direction of the default read voltage to a negative direction when the number of read cells is equal to or larger than the reference cell number.

### Claim 3 (depends on 2)

The apparatus of claim 2, wherein when the shift direction is set to the positive direction, the processor controls the read retry operation of the memory device while sequentially selecting read voltages in the positive direction in the table.

### Claim 4 (depends on 3)

The apparatus of claim 3, wherein when the shift direction is set to the negative direction, the processor controls the read retry operation of the memory device while sequentially selecting read voltages in the negative direction in the table.

### Claim 5 (depends on 4)

The apparatus of claim 4, wherein the error correction unit corrects an error of data read from the memory device through the read retry operation, and
when the error correction of the error correction unit is normally performed, the processor sets the corresponding read voltage to a read voltage of the memory device.

### Claim 6 (depends on 2)

The apparatus of claim 2, wherein the table stores read voltages of single level cells (SLCs), and
the processor selects a default read voltage R1 among default read voltages R1 to R7 stored in the table when the read fail is recognized, and sets the shift direction of the default read voltage R1 by analyzing the number of erased cells read from the memory device based on the default read voltage R1.

### Claim 7 (depends on 2)

The apparatus of claim 2, wherein the table stores read voltages of multi-level cells (MLCs), and
when the read fail is recognized, the processor analyzes a page type in the memory device, and selects a default read voltage of the analyzed page type in the table.

### Claim 8 (depends on 7)

The apparatus of claim 7, wherein when the page type is a least significant bit (LSB) type, the processor selects a default read voltage R1 and/or R3 among default read voltages R1 to R7 stored in the table, and sets the shift direction of the default read voltages R1 and R3 by analyzing the number of LSB cells read from the memory device based on the default read voltage R1 and/or R3, and
when the page type is a most significant bit (MSB) type, the processor selects a default read voltage R2 in the table, and sets the shift direction of the default read voltage R2 by analyzing the number of MSB cells read from the memory device based on the default read voltage R2.

### Claim 9 (depends on 2)

The apparatus of claim 2, wherein the RR table stores read voltages of triple level cells (TLCs), and
when the read fail is recognized, the processor analyzes a page type in the memory device, and selects a default read voltage of the analyzed page type in the table.

### Claim 10 (depends on 9)

The apparatus of claim 9, wherein when the page type is a least significant bit (LSB) type, the processor selects a default read voltage R3 and/or R7 among default read voltages R1 to R7 stored in the table, and sets the shift direction of the default read voltages R3 and R7 by analyzing the number of LSB cells read from the memory device based on the default read voltage R3 and/or R7,
when the page type is a center significant bit (CSB) type, the processor selects a default read voltage R2, R4 and/or R6 in the table, and sets the shift direction of the default read voltages R2, R4 and R6 by analyzing the number of CSB cells read from the memory device based on the default read voltage R2, R4 and/or R6, and
when the page type is a most significant bit (MSB) type, the processor selects a default read voltage R1 and/or R5 in the table, and sets the shift direction of the default read voltages R1 and R5 by analyzing the number of MSB cells read from the memory device based on the default read voltage R1 and/or R5.

### Claim 11

A method for controlling a memory device, comprising:
selecting a default read voltage from a table storing information of a plurality of read voltages when a read fail for the memory device is recognized;
generating and using the default read voltage to read cells of the memory device;
setting a shift direction of the default read voltage based on a count of read cells for determining a next read voltage in the table; and
generating and using the next read voltage to read the cells of the memory device for the read retry operation.

### Claim 12 (depends on 11)

The method of claim 11, wherein the setting of the shift direction of the default read voltage comprises:
comparing the number of read cells to a reference cell number, based on the default read voltage;
setting the shift direction of the default read voltage to a positive direction when the number of read cells is smaller than the reference cell number; and
setting the shift direction of the default read voltage to a negative direction when the number of read cells is equal to or larger than the reference cell number.

### Claim 13 (depends on 12)

The method of claim 12, wherein the controlling of the read retry operation comprises controlling the read retry operation of the memory device while sequentially selecting read voltages in the positive direction in the table, when the shift direction of the default read voltage is set to the positive direction.

### Claim 14 (depends on 13)

The method of claim 13, wherein the controlling of the read retry operation comprises controlling the read retry operation of the memory device while sequentially selecting read voltages in the negative direction in the table, when the shift direction of the default read voltage is set to the negative direction.

### Claim 15 (depends on 14)

The method of claim 14, wherein the controlling of the read retry operation comprises:
correcting an error of data read from the memory device; and
setting the corresponding read voltage to a read voltage of the memory device when the error correction is normally performed.

### Claim 16 (depends on 11)

The method of claim 11, wherein the table stores read voltages of single level cells (SLCs), and
wherein the selecting of the default read voltage of the table comprises selecting a default read voltage R1 among default read voltages R1 to R7 stored in the table when a read fail is recognized, and
the setting of the shift direction of the reference read voltage comprises setting the shift direction of the default read voltage by analyzing the number of erased cells read from the memory device based on the default read voltage R1.

### Claim 17 (depends on 11)

The method of claim 11, wherein the table stores read voltages of multi-level cells (MLCs), and
the selecting of the default read voltage of the table comprises:
analyzing a page type in the memory device when the read fail is recognized; and
selecting a default read voltage of the analyzed page type in the table.

### Claim 18 (depends on 17)

The method of claim 17, wherein the setting of the shift direction of the default read voltage comprises:
selecting a default read voltage R1 and/or R3 among default read voltages R1 to R7 stored in the table when the page type is a least significant bit (LSB) type, and setting the shift direction of the default read voltages R1 and R3 by analyzing the number of LSB cells read from the memory device based on the default read voltage R1 and/or R3; and
selecting a default read voltage R2 in the table when the page type is a most significant bit (MSB) type, and setting the shift direction of the default read voltage R2 by analyzing the number of MSB cells read from the memory device based on the default read voltage R2.

### Claim 19 (depends on 11)

The method of claim 11, wherein the table stores read voltages of triple level cells (TLCs), and
the selecting of the default read voltage of the table comprises:
analyzing a page type in the memory device when the read fail is recognized; and
selecting a default read voltage of the analyzed page type in the table.

### Claim 20 (depends on 19)

The method of claim 19, wherein the setting of the shift direction of the default read voltage comprises:
selecting a default read voltage R3 and/or R7 among default read voltages R1 to R7 stored in the table when the page type is a least significant bit (LSB) type, and setting the shift direction of the default read voltages R3 and R7 by analyzing the number of LSB cells read from the memory device based on the default read voltage R3 and/or R7;
selecting a default read voltage R2, R4 and/or R6 in the table when the page type is a center significant bit (CSB) type, and setting the shift direction of the default read voltages R2, R4 and R6 by analyzing the number of CSB cells read from the memory device based on the default read voltage R2, R4 and/or R6; and
selecting a default read voltage R1 and/or R5 in the table when the page type is a most significant bit (MSB) type, and setting the shift direction of the default read voltages R1 and R5 by analyzing the number of MSB cells read from the memory device based on the default read voltage R1 and/or R5.