# US 10,311,832 B2 · System-on-chip (SoC) devices, display drivers and SoC systems including the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,832 B2 - Document ID: US10311832B2 - Status: Granted - Kind: B2 - Application number: 15/991,227 - Filed: 2018-05-29 - Published: 2018-09-27 - Granted: 2019-06-04 - Earliest claimed: 2014-09-12 - Assignees: Samaung Electronics Co., Ltd. - Applicants: Samsung Electronics Co., Ltd. - Inventors: Jong-Hyup Lee; Kyoung-Man Kim - Web page: https://patentgrep.com/patent/US10311832B2 ## CPC - G09G 5/12: Synchronisation between the display unit and other units, e.g. other display units, video-disc players - G09G 3/2096: {Details of the interface to the display terminal specific for a flat panel (suitable for both CRT and flat panel G09G5/006; specific for a CRT G09G1/167)} - G09G 3/3648: {using an active matrix (G09G3/367 - G09G3/3696 take precedence)} - G09G 3/3685: {Details of drivers for data electrodes} - G09G 5/006: {Details of the interface to the display terminal (specific for a display terminal using a CRT G09G1/167; using a flat panel G09G3/2096; circuits for interfacing with colour displays G09G5/04)} - G09G 5/18: Timing circuits for raster scan displays (specially adapted for television H04N {; synchronisation between the display unit and other display units, videodisc player G09G5/12}) - G09G 5/363: {Graphics controllers} - G09G 5/39: Control of the bit-mapped memory - G09G 5/393: Arrangements for updating the contents of the bit-mapped memory - G09G 2330/021: Power management, e.g. power saving - G09G 2330/022: in absence of operation, e.g. no data being entered during a predetermined time - G09G 2360/18: Use of a frame buffer in a display terminal, inclusive of the display panel - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) ## Abstract A system-on-chip (SoC) device includes: a display controller configured to receive a trigger signal, and to output image data based on the trigger signal; and a transceiver configured to receive a first interrupt. In a first mode, the display controller is configured to output the image data in synchronization with a pulse of the trigger signal. In a second mode, which is different from the first mode, the display controller is configured to output the image data in synchronization with a pulse included in the trigger signal only after receiving the first interrupt. ## Claims ### Claim 1 A system-on-chip (SoC) system comprising: a SoC device configured to receive a trigger signal and a first interrupt signal, and to output image data based on the trigger signal and the first interrupt signal, wherein in a first mode, the SoC device is configured to transmit first image data in synchronization with a pulse of the trigger signal, in a second mode, the SoC device is configured to transmit second image data in synchronization with a pulse of the trigger signal only after receiving the first interrupt signal, and the trigger signal and the first interrupt signal are synchronized with each other; and a display configured to transmit the trigger signal and the first interrupt signal to the SoC device, and to output the first image data and the second image data in the first mode and the second mode, respectively, wherein the display is configured to transmit the first interrupt signal to the SoC device only in the second mode. ### Claim 2 (depends on 1) The SoC system of claim 1, wherein the first image data includes moving image data; and the second image data includes still image data. ### Claim 3 (depends on 1) The SoC system of claim 1, wherein a frequency of the trigger signal is greater than a frequency of the first interrupt signal. ### Claim 4 (depends on 1) The SoC system of claim 1, wherein the display is further configured to transmit a second signal to the SoC device only in the second mode to change the second mode to the first mode. ### Claim 5 (depends on 1) The SoC system of claim 1, wherein the display comprises an IGZO(Indium Gallium Zinc Oxide) panel. ### Claim 6 (depends on 5) The SoC system of claim 5, wherein the display is further configured to switch from the first mode to the second mode based on whether the SOC device has continuously transmitted the same image data p times, and p is a natural number greater than or equal to 2. ### Claim 7 (depends on 6) The SoC system of claim 6, wherein the display is further configured to transmit the first interrupt signal to the SoC device after switching from the first mode to the second mode. ### Claim 8 (depends on 1) The SoC system of claim 1, wherein a frame rate of the display in the first mode is greater than a frame rate of the display in the second mode. ### Claim 9 (depends on 1) The SoC system of claim 1, further comprising external memory storing the first image data and the second image data. ### Claim 10 A system-on-chip (SoC) system comprising: a SoC device configured to receive a trigger signal including successive first and second pulses, transmit first still image data in synchronization with the first pulse, and transmit second still image data in synchronization with the second pulse; and a display configured to transmit the trigger signal to the SoC device, receive the first still image data and the second still image data from the SoC device, output the first still image data in synchronization with the first pulse, output the second still image data in synchronization with the second pulse, generate a first interrupt signal in response to determining that the first still image data and the second still image data are identical, and transmit the first interrupt signal to the SoC device, wherein the SoC device is further configured to wait until the first interrupt signal is received, and transmit the second still image data to the display in response to receiving the first interrupt signal from the display, and wherein the trigger signal and the first interrupt signal are synchronized with each other. ### Claim 11 (depends on 10) The SoC system of claim 10, wherein the display comprises an IGZO(Indium Gallium Zinc Oxide) panel. ### Claim 12 (depends on 10) The SoC system of claim 10, wherein a frequency of the trigger signal is greater than a frequency of the first interrupt signal. ### Claim 13 (depends on 10) The SoC system of claim 10, wherein a frame rate of the display in a first mode is greater than a frame rate of the display in a second mode. ### Claim 14 A system-on-chip (SoC) system comprising: a SoC device configured to receive a trigger signal including successive first and second pulses, transmit first still image data in synchronization with the first pulse, and transmit second still image data in synchronization with the second pulse; and a display configured to transmit the trigger signal to the SoC device, receive the first still image data and the second still image data from the SoC device, output the first still image data in synchronization with the first pulse, output the second still image data in synchronization with the second pulse, generate a first interrupt signal in response to determining that the first still image data and the second still image data are identical, and transmit the first interrupt signal to the SoC device, wherein the SoC device is further configured to wait until the first interrupt signal is received, and transmit the second still image data to the display in response to receiving the first interrupt signal from the display, wherein the trigger signal includes third to fifth pulses that are continuous with the first and second pulses, and the SoC device is further configured to receive the first interrupt signal from the display in synchronization with the fourth pulse. ### Claim 15 (depends on 14) The SoC system of claim 14, wherein the SoC device is configured to not transmit any still image data to the display. ### Claim 16 (depends on 14) The SoC system of claim 14, wherein the SoC device is configured to transmit the second still image data to the display in synchronization with the fifth pulse. ### Claim 17 (depends on 14) The SoC system of claim 14, wherein the display is configured to generate a second interrupt signal when an event occurs after the fifth pulse has passed, and transmit the second interrupt signal to the SoC device. ### Claim 18 (depends on 17) The SoC system of claim 17, wherein the trigger signal includes successive sixth and seventh pulses after the fifth pulse; and the SoC device is configured to receive the second interrupt signal, transmit third still image data in synchronization with the sixth pulse, and transmit fourth still image data in synchronization with the seventh pulse.