# US 10,311,811 B2 · Array substrate, display device and driving method > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,811 B2 - Document ID: US10311811B2 - Status: Granted - Kind: B2 - Application number: 15/311,899 - Filed: 2016-01-26 - Published: 2018-07-05 - Granted: 2019-06-04 - Earliest claimed: 2015-08-28 - Assignees: Boe Technology Group Co., Ltd.; Chongqing Boe Optoelectronics Technology Co., Ltd. - Applicants: Boe Technology Group Co., Ltd.; Chongqing Boe Optoelectronics Technology Co., Ltd. - Inventors: Xiaoyuan Wang; Wu Wang; Jaikwang Kim; Zhuo Xu; Yajie Bai - Web page: https://patentgrep.com/patent/US10311811B2 ## CPC - G09G 3/3611: {Control of matrices with row and column drivers} - G02F 1/133: Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements (arrangements or circuits for control of liquid crystal elements in a matrix, not structurally associated with these elements G09G3/36) - G02F 1/13306: {Circuit arrangements or driving methods for the control of single liquid crystal cells (G02F1/132, G02F1/133382 take precedence)} - G02F 1/1343: Electrodes {(reflective electrodes G02F1/133553)} - G02F 1/1362: Active matrix addressed cells {(G02F1/134336, G02F1/134363 take precedence)} - G02F 1/136286: {Wiring, e.g. gate line, drain line} - G02F 1/1368: in which the switching element is a three-electrode device {(G02F1/136277 takes precedence)} - G09G 3/3614: {Control of polarity reversal in general} - G09G 3/3659: {the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes} - G09G 2300/0426: Layout of electrodes and connections - G09G 2310/0264: Details of driving circuits - G09G 2320/0247: Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G02F: OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS ## Abstract The array substrate comprises a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction crossing the first direction, and a plurality of pixel units arranged as an array. Each of the plurality of data lines is arranged between two columns of pixel units, the two columns of the pixel units extending in the second direction and being adjacent to each other in the first direction, and the data line is connected to pixel units at one side of said data line or to pixel units at the other side of said data line. Each of the plurality of data lines switches the direction of connection from one side to the other in an alternating manner with each two adjacent rows of pixel units, and the plurality of data lines have the same connection direction in each row of pixel units. ## Claims ### Claim 1 An array substrate, comprising a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction crossing the first direction, and a plurality of pixel units arranged as an array along the first direction and the second direction, wherein, each of the plurality of data lines is arranged between two columns of the pixel units, the two columns of the pixel units extending in the second direction and being adjacent to each other in the first direction, and each of the plurality of data lines is connected to immediately adjacent pixel units; and each of the plurality of data lines switches a connection direction from one side to the other in an alternating manner with each two adjacent rows of pixel units, and the plurality of data lines have the same connection direction in each row of pixel units, wherein each pixel unit includes a first pixel electrode and a second pixel electrode, as well as a first thin film transistor and a second thin film transistor corresponding to the first pixel electrode and the second pixel electrode, respectively, the first pixel electrode and the second pixel electrode being respectively connected to respective drains of the first thin film transistor and the second thin film transistor, two gate lines corresponding to one row of pixel units are respectively connected to respective gates of the first thin film transistor and the second thin film transistor in said row of pixel units, connection relationship between gate lines and the first and the second thin film transistors being changed once every two rows of pixel units, the data lines are connected to the corresponding pixel units through respective sources of the first thin film transistor and the second thin film transistor. ### Claim 2 (depends on 1) The array substrate according to claim 1, wherein each of the plurality of gate lines corresponds to a row of pixel units extending in the first direction. ### Claim 3 (depends on 2) The array substrate according to claim 2, wherein each pixel unit includes a pixel electrode and a thin film transistor, the pixel electrode being connected to a drain of the thin film transistor, one of the plurality of gate lines being connected to the pixel unit through a gate of the thin film transistor, and one of the plurality of data lines being connected to the corresponding pixel unit through a source of the thin film transistor. ### Claim 4 (depends on 1) The array substrate according to claim 1, wherein every two gate lines correspond to a row of pixel units extending in the first direction, and are respectively arranged at two sides of said row of pixel units in the second direction. ### Claim 5 (depends on 1) The array substrate according to claim 1, wherein the first pixel electrode and the second pixel electrode are arranged in the pixel units along the first direction. ### Claim 6 (depends on 1) The array substrate according to claim 1, wherein one of the two gate lines corresponding to a row of pixel units is connected to a gate of each of the first thin film transistors in said row of pixel units, while the other one of the two gate lines corresponding to the row of pixel units is connected to a gate of each of the second thin film transistors in said row of pixel units. ### Claim 7 (depends on 1) The array substrate according to claim 1, wherein the polarities of output signals on each data line remain unchanged within one frame, and the polarities of output signals on two data lines adjacent in the first direction are opposite. ### Claim 8 (depends on 7) The array substrate according to claim 7, wherein the polarities of output signals on each data line are inverted once between two adjacent frames. ### Claim 9 (depends on 1) A display device, which comprises the array substrate according to claim 1. ### Claim 10 (depends on 9) The display device according to claim 9, wherein each of the plurality of gate lines corresponds to a row of pixel units extending in the first direction. ### Claim 11 (depends on 10) The display device according to claim 10, wherein each pixel unit includes a pixel electrode and a thin film transistor, the pixel electrode being connected to a drain of the thin film transistor, one of the plurality of gate lines being connected to the pixel unit through a gate of the thin film transistor, and one of the plurality of data lines being connected to the corresponding pixel unit through a source of the thin film transistor. ### Claim 12 (depends on 9) The display device according to claim 9, wherein every two gate lines correspond to a row of pixel units extending in the first direction, and are respectively arranged at two sides of said row of pixel units in the second direction. ### Claim 13 (depends on 9) The display device according to claim 9, wherein the first pixel electrode and the second pixel electrode are arranged in the pixel units along the first direction. ### Claim 14 (depends on 9) The display device according to claim 9, wherein one of the two gate lines corresponding to a row of pixel units is connected to a gate of each of the first thin film transistors in said row of pixel units, while the other one of the two gate lines corresponding to the row of pixel units is connected to a gate of each of the second thin film transistors in said row of pixel units. ### Claim 15 (depends on 9) The display device according to claim 9, wherein the polarities of output signals on each data line remain unchanged within one frame, and the polarities of output signals on two data lines adjacent in the first direction are opposite. ### Claim 16 (depends on 15) The display device according to claim 15, wherein the polarities of output signals on each data line are inverted once between two adjacent frames. ### Claim 17 A method of driving the array substrate, the array substrate comprising a plurality of gate lines extending in a first direction, a plurality of data lines extending in a second direction crossing the first direction, and a plurality of pixel units arranged as an array along the first direction and the second direction, wherein each of the plurality of data lines is arranged between two columns of the pixel units, the two columns of the pixel units extending in the second direction and being adjacent to each other in the first direction, and each of the plurality of data lines is connected to immediately adjacent pixel units; and wherein each of the plurality of data lines switches a connection direction from one side to the other in an alternating manner with each two adjacent rows of pixel units, and the plurality of data lines have the same connection direction in each row of pixel units, the method comprising: keeping the polarities of output signals on each data line unchanged within one frame, and making the polarities of output signals on two data lines adjacent in the first direction to be opposite, so that a voltage applied to the pixel units has a polarity inversion in the first direction using one pixel unit as a period and in the second direction using two pixel units as a period, wherein each pixel unit includes a first pixel electrode and a second pixel electrode, as well as a first thin film transistor and a second thin film transistor corresponding to the first pixel electrode and the second pixel electrode, respectively, the first pixel electrode and the second pixel electrode being respectively connected to respective drains of the first thin film transistor and the second thin film transistor, two gate lines corresponding to one row of pixel units are respectively connected to respective gates of the first thin film transistor and the second thin film transistor in said row of pixel units, connection relationship between gate lines and the first and the second thin film transistors being changed once every two rows of pixel units, the data lines are connected to the corresponding pixel units through respective sources of the first thin film transistor and the second thin film transistor. ### Claim 18 (depends on 17) The method according to claim 17, wherein the polarities of output signals on each data line are inverted once between two adjacent frames.