# US 10,311,795 B2 · Shift register unit, gate driver circuit and display device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,795 B2 - Document ID: US10311795B2 - Status: Granted - Kind: B2 - Application number: 15/325,137 - Filed: 2016-08-09 - Published: 2018-06-28 - Granted: 2019-06-04 - Earliest claimed: 2016-01-05 - Assignees: Boe Technology Group Co., Ltd.; Beijing Boe Display Technology Co., Ltd. - Applicants: Boe Technology Group Co., Ltd.; Beijing Boe Display Technology Co., Ltd. - Inventors: Huabin Chen; Ruirui Wang; Yingqiang Gao; Xiaopeng Cui - Web page: https://patentgrep.com/patent/US10311795B2 ## CPC - G09G 3/3266: Details of drivers for scan electrodes - G09G 3/20: for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} - G09G 3/3674: {Details of drivers for scan electrodes} - G11C 19/28: using semiconductor elements (G11C19/14, G11C19/36 take precedence) - G09G 2310/0267: Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/061: for resetting or blanking - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A shift register unit is disclosed which includes an input module, a reset module, a node control module, a first output module and a second output module. Each of the shift register units can output two scan signals that have a phase difference with respect to each other. Also disclosed are a gate driver circuit and a display device. ## Claims ### Claim 1 A shift register unit comprising: an input terminal, a reset terminal, a reference terminal, a first clock terminal, a second clock terminal, a third clock terminal, a first output terminal, a second output terminal, an input circuit for receiving an input signal from the input terminal and providing the input signal to a first node as a first level voltage; a first reset circuit for receiving a reference voltage from the reference terminal, and providing the reference voltage to the first node as a second level voltage in response to a reset signal from the reset terminal, the second level voltage being logically opposite to the first level voltage; a node control circuit for receiving a third clock signal from the third clock terminal and the reference voltage, and providing at a second node a second voltage signal logically opposite to a first voltage signal at the first node, the first voltage signal comprising a portion having the first level voltage and a portion having the second level voltage; a first output circuit for receiving a first clock signal from the first clock terminal and the reference voltage, and selectively providing the first clock signal or the reference voltage to the first output terminal in response to first voltage signal and the second voltage signal; and a second output circuit for receiving a second clock signal from the second clock terminal and the reference voltage, selectively providing the second clock signal or the reference voltage to the second output terminal in response to the first voltage signal and the second voltage signal, and maintaining a voltage difference between the first node and the second output terminal when the first node is floated, wherein the node control circuit comprises: a first node control circuit for providing the reference voltage to the first node in response to the second voltage signal; and a second node control circuit for providing at the second node the second voltage signal in response to the third clock signal and the first voltage signal. ### Claim 2 (depends on 1) The shift register unit of claim 1, wherein the first clock signal and the second clock signal have a phase difference of 90° with respect to each other, and wherein the third clock signal and the second clock signal have phases opposite to each other. ### Claim 3 (depends on 2) A gate driver circuit comprising a plurality of shift register units as recited in claim 2 that are cascaded with each other, wherein the input terminal of the first stage of shift register unit is configured to receive a start signal; the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit. ### Claim 4 (depends on 1) The shift register unit of claim 1, wherein the first node control circuit comprises a seventh transistor having a source connected to the reference terminal, a gate connected to the second node, and a drain connected to the first node. ### Claim 5 (depends on 4) A gate driver circuit comprising a plurality of shift register units as recited in claim 4 that are cascaded with each other, wherein the input terminal of the first stage of shift register unit is configured to receive a start signal; the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit. ### Claim 6 (depends on 1) The shift register unit of claim 1, wherein the second node control circuit comprises: an eighth transistor having a source and a gate jointly connected to the third clock terminal, and a drain; a ninth transistor having a source connected to the third clock terminal, a gate connected to the drain of the eighth transistor, and a drain connected to the second node; a tenth transistor having a source connected to the reference terminal, a gate connected to the first node, and a drain connected to the drain of the eighth transistor; and an eleventh transistor having a source connected to the reference terminal, a gate connected to the first node, and a drain connected to the second node. ### Claim 7 (depends on 1) The shift register unit of claim 1, wherein the input circuit comprises a first transistor having a source and a gate jointly connected to the input terminal and a drain connected to the first node. ### Claim 8 (depends on 4) A gate driver circuit comprising a plurality of shift register units as recited in claim 4 that are cascaded with each other, wherein the input terminal of the first stage of shift register unit is configured to receive a start signal; the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit. ### Claim 9 (depends on 1) The shift register unit of claim 1, wherein the first reset circuit comprises a second transistor having a source connected to the reference terminal, a gate connected to the reset terminal, and a drain connected to the first node. ### Claim 10 (depends on 9) A gate driver circuit comprising a plurality of shift register units as recited in claim 9 that are cascaded with each other, wherein the input terminal of the first stage of shift register unit is configured to receive a start signal; the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit. ### Claim 11 (depends on 1) The shift register unit of claim 1, wherein the first output circuit comprises: a third transistor having a source connected to the first clock terminal, a gate connected to the first node, and a drain connected to the first output terminal; and a fourth transistor having a source connected to the reference terminal, a gate connected to the second node, and a drain connected to the first output terminal. ### Claim 12 (depends on 11) A gate driver circuit comprising a plurality of shift register units as recited in claim 11 that are cascaded with each other, wherein the input terminal of the first stage of shift register unit is configured to receive a start signal; the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit. ### Claim 13 (depends on 1) The shift register unit of claim 1, wherein the second output circuit comprises: a fifth transistor having a source connected to the second clock terminal, a gate connected to the first node, and a drain connected to the second output terminal; a sixth transistor having a source connected to the reference terminal, a gate connected to the second node, and a drain connected to the second output terminal; and a capacitor connected between the first node and the second output terminal. ### Claim 14 (depends on 13) A gate driver circuit comprising a plurality of shift register units as recited in claim 13 that are cascaded with each other, wherein the input terminal of the first stage of shift register unit is configured to receive a start signal; the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit. ### Claim 15 (depends on 1) The shift register unit of claim 1, further comprising a second reset circuit for providing the reference voltage to the second output terminal in response to the reset signal. ### Claim 16 (depends on 15) The shift register unit of claim 15, wherein the second reset circuit comprises a twelfth transistor having a source connected to the reference terminal, a gate connected to the reset terminal, and a drain connected to the second output terminal. ### Claim 17 (depends on 1) A gate driver circuit comprising a plurality of shift register units as recited in claim 1 that are cascaded with each other, wherein the input terminal of the first stage of shift register unit is configured to receive a start signal; the input terminal of each of the shift register units except for the first stage of shift register unit is connected to the second output terminal of a previous stage of shift register unit; and the reset terminal of each of the shift register units except for the last stage of shift register unit is connected to the second output terminal of a next stage of shift register unit. ### Claim 18 (depends on 17) A display device comprising: a display panel comprising 2N gate lines, wherein N is a positive integer; and a gate driver circuit as recited in claim 17, wherein the first output terminal and the second output terminal of the n-th stage of shift register unit of the gate driver circuit are connected to the (2n−1)th gate line and the 2n-th gate line, respectively, wherein n is a positive integer and 1≤n≤N.