# US 10,311,791 B2 · Pixel circuit, display device, and method for driving same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,791 B2 - Document ID: US10311791B2 - Status: Granted - Kind: B2 - Application number: 15/579,989 - Filed: 2016-06-29 - Published: 2018-06-21 - Granted: 2019-06-04 - Earliest claimed: 2015-07-10 - Assignees: Sharp Kabushiki Kaisha - Applicants: Sharp Kabushiki Kaisha - Inventors: Masanori Ohara; Hideki Uchida; Katsuhiro Kikuchi; Satoshi Inoue; Yuto Tsukamoto; Eiji Koike; Kazuo Takizawa; Noboru Noguchi; Noritaka Kishi - Web page: https://patentgrep.com/patent/US10311791B2 ## CPC - G09G 3/3233: with pixel circuitry controlling the current through the light-emitting element - G09G 3/325: the data current flowing through the driving transistor during a setting phase, e.g. by using a switch for connecting the driving transistor to the data driver - G09G 3/3266: Details of drivers for scan electrodes - H10K 59/127: comprising two substrates, e.g. display comprising OLED array and TFT driving circuitry on different substrates - G09G 2300/0819: used for counteracting undesired variations, e.g. feedback or autozeroing - G09G 2310/0278: Details of driving circuits arranged to drive both scan and data electrodes - G09G 2310/0286: Details of a shift registers arranged for use in a driving circuit - G09G 2310/0289: Details of voltage level shifters arranged for use in a driving circuit - G09G 2310/0294: Details of sampling or holding circuits arranged for use in a driver for data electrodes - G09G 2310/0297: Special arrangements with multiplexing or demultiplexing of display data in the drivers for data electrodes, in a pre-processing circuitry delivering display data to said drivers or in the matrix panel, e.g. multiplexing plural data signals to one D/A converter or demultiplexing the D/A converter output to multiple columns - G09G 2310/06: Details of flat display driving waveforms - G09G 2320/0219: Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling - G09G 2320/0276: for the purpose of adaptation to the characteristics of a display device, i.e. gamma correction - G09G 2320/0295: by monitoring each display pixel - G09G 2330/12: Test circuits or failure detection circuits included in a display system, as permanent part thereof - G09G 2360/16: Calculation or use of calculated indices related to luminance levels in display data - G09G: ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION (arrangements for transferring data between digital computers and displays G06F3/14; static indicating arrangements comprising an association of a number of separate sources or light control cells G09F9/00; static indicating arrangements comprising integral associations of a number of light sources H01J, H01K, H10H, H05B33/12; scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission, details thereof H04N1/00) - H10K: ORGANIC ELECTRIC SOLID-STATE DEVICES ## Abstract The purpose of the present invention is to suppress the fluctuation of a data line voltage that occurs when an analog voltage signal is sampled and held in a data line in a display device provided with a current-driven display element. Transistors (SWr, SWG, SWb) of each demultiplexer (252) are successively switched on, for each predetermined period, in a selection period of a write control line (SW_LR(i)). In a period when the transistor (SWr) is switched on, an analog video signal (Dj) from a data voltage output unit circuit (211d) is applied to a data line (SLrj) and a pixel circuit (50r). When the transistor SWr is then switched off, the voltage held by the data line (SLrj) decreases below the voltage of the analog video signal (Dj) due to a parasitic capacitance (Cssdr). However, the voltage of a voltage fluctuation compensation line (G3_Cnt (i)) changes from a low level to a high level within the selection period. This causes the voltage of the data line (SLrj) to rise via a capacitor (Ccnt), and the decrease in voltage to be compensated for. ## Claims ### Claim 1 A pixel circuit in a display device, the display device including a plurality of data lines through which a plurality of analog voltage signals representing an image to be displayed are transmitted; a plurality of write control lines crossing the plurality of data lines; and a plurality of display elements driven by a current and arranged in a matrix along the plurality of data lines and the plurality of write control lines, the display device including a function of measuring a drive current to be applied to each display element, and the pixel circuit being arranged to correspond to any one of the plurality of data lines and correspond to any one of the plurality of write control lines, the pixel circuit comprising: an electro-optical element with a brightness controlled by a current, the electro-optical element being one of the plurality of display elements; a voltage holding capacitor that holds a data voltage to control a drive current of the electro-optical element; an input transistor including a control terminal connected to a corresponding write control line, the input transistor being a switching element that controls a voltage supply from a corresponding data line to the voltage holding capacitor; a drive transistor that applies a drive current corresponding to the data voltage to the electro-optical element; a monitor control transistor including a control terminal connected to a predetermined monitor control line arrayed along the corresponding write control line, the monitor control transistor being arranged between the drive transistor and the corresponding data line to allow a current flowing through the drive transistor to pass through; a voltage fluctuation compensation transistor including a control terminal connected to a predetermined voltage fluctuation compensation line arrayed along the corresponding write control line and a first conduction terminal connected to the corresponding data line, the voltage fluctuation compensation transistor being connected in series to the monitor control transistor; and a voltage fluctuation compensation capacitor defined between the first conduction terminal in the voltage fluctuation compensation transistor and the control terminal in the voltage fluctuation compensation transistor, wherein the voltage fluctuation compensation transistor changes from an off state to an on state in a period during which the input transistor is in an on state. ### Claim 2 (depends on 1) A display device including a plurality of data lines through which to transmit a plurality of analog voltage signals representing an image to be displayed; a plurality of write control lines crossing the plurality of data lines; and a plurality of display elements driven by a current and arranged in a matrix along the plurality of data lines and the plurality of write control lines, the display device including a function of measuring a drive current to be applied to each display element, the display device comprising: a plurality of the pixel circuits according to claim 1 arranged in the matrix along the plurality of data lines and the plurality of write control lines with each of the plurality of pixel circuits being corresponded to any one of the plurality of data lines and corresponded to any one of the plurality of write control lines; a plurality of monitor control lines arrayed along the plurality of write control lines to correspond to each of the plurality of write control lines; a plurality of voltage fluctuation compensation lines arrayed along the plurality of write control lines to correspond to each of the plurality of write control lines; a plurality of connection control transistors corresponding to each of the plurality of data lines, each of the plurality of connection control transistors including a first conduction terminal connected to a corresponding data line, a second conduction terminal that receives an analog voltage signal to be applied to the corresponding data line, and a control terminal that receives a connection control signal to control switching on and off; a data line drive circuit that applies the analog voltage signal to the second conduction terminal of each of the plurality of connection control transistors; a write control line drive circuit that selectively drives the plurality of write control lines; a monitor control line drive circuit that selectively drives the plurality of monitor control lines; a voltage fluctuation compensation line drive circuit that selectively drives the plurality of voltage fluctuation compensation lines; a current measurement circuit that measures, via the plurality of data lines and the plurality of connection control transistors, a drive current to be applied to a display element in each pixel circuit; and drive control circuitry that controls the plurality of connection control transistors, the write control line drive circuit, the monitor control line drive circuit, and the voltage fluctuation compensation line drive circuit; wherein the data line drive circuit includes a predetermined number of output terminals respectively corresponding to a plurality of sets of data line groups obtained by grouping the plurality of data lines with one set includes a predetermined number of two or more data lines, each output terminal is connected to a second conduction terminal of a predetermined number of connection control transistors corresponding to a predetermined number of data lines of a corresponding set, the drive control circuitry generates a predetermined number of connection control signals respectively corresponding to a predetermined number of data lines of each set and respectively applies the predetermined number of connection control signals to the control terminals of the predetermined number of connection control transistors corresponding to a predetermined number of data lines of each set to thereby successively switch on the predetermined number of connection control transistors of each set for each predetermined period in a first selection period during which any one of the plurality of write control lines is in a selected state, and in the first selection period, the voltage fluctuation compensation line drive circuit changes, after the plurality of connection control transistors are changed from an on state to an off state, a voltage to be applied to a voltage fluctuation compensation line corresponding to a write control line in the selected state from a first voltage to a second voltage to thereby change a voltage of the corresponding voltage fluctuation compensation line in direction opposite to a change of a voltage to be applied to the control terminals of the plurality of connection control transistors to change the plurality of connection control transistors from an on state to an off state. ### Claim 3 (depends on 2) The display device according to claim 2, wherein the voltage fluctuation compensation line drive circuit returns, in a period during which the plurality of write control lines are in a non-selected state after the first selection period, the voltage of the voltage fluctuation compensation line corresponding to the write control line in the selected state in the first selection period from the second voltage to the first voltage. ### Claim 4 (depends on 2) The display device according to claim 2, wherein the voltage fluctuation compensation line drive circuit returns, in a period during which a write control line selected subsequently to the write control line in the selected state in the first selection period is in the selected state, the voltage of the voltage fluctuation compensation line corresponding to the write control line in the selected state in the first selection period from the second voltage to the first voltage, before the connection control transistor first changing from an on state to an off state starts the change to the off state. ### Claim 5 (depends on 2) The display device according to claim 2, further comprising: a voltage source that supplies the first voltage and the second voltage to the voltage fluctuation compensation line drive circuit, wherein a difference between the first voltage and the second voltage is changeable. ### Claim 6 (depends on 2) The display device according to claim 2, wherein the first voltage and the second voltage are set to cancel out a voltage fluctuation in the plurality of data lines occurring as a result of the plurality of connection control transistors being changed from an on state to an off state in the first selection period, by a change from the first voltage to the second voltage of the voltage of the voltage fluctuation compensation line corresponding to the write control line in the selected state in the first selection period. ### Claim 7 (depends on 2) The display device according to claim 2, wherein upon measurement of a drive current to be applied to a display element in a pixel circuit corresponding to any one write control line of the plurality of write control lines, the drive control circuitry: controls, in a non-selection period, during the non-selection period the plurality of write control lines being in a non-selected state, the non-selection period occurring immediately after a second selection period, during the second selection period the one write control line being selected, the monitor control line drive circuit and the voltage fluctuation compensation line drive circuit to cause a monitor control transistor and a voltage fluctuation compensation transistor in the pixel circuit corresponding to the one write control line to be switched on; and applies the predetermined number of connection control signals to the control terminals of the predetermined number of connection control transistors corresponding to a predetermined number of data lines of each set to thereby successively switch on the predetermined number of connection control transistors of each set for each predetermined period in the non-selection period, and the current measurement circuit measures a current flowing through a drive transistor in the pixel circuit corresponding to the one write control line via a switched-on transistor out of the monitor control transistor, the voltage fluctuation compensation transistor, and the predetermined number of connection control transistors of each set. ### Claim 8 (depends on 2) The display device according to claim 2, wherein a transistor included in each pixel circuit and the plurality of connection control transistors are thin film transistors with a channel layer made of an oxide semiconductor. ### Claim 9 A driving method of a display device, the display device including a plurality of data lines through which to transmit a plurality of analog voltage signals representing an image to be displayed; a plurality of write control lines intersecting the plurality of data lines; a plurality of display elements driven by a current and arranged in a matrix along the plurality of data lines and the plurality of write control lines; and a plurality of connection control transistors arranged to correspond to each of the plurality of data lines, each of the plurality of connection control transistors including a first conduction terminal connected to a corresponding data line, a second conduction terminal that receives an analog voltage signal to be applied to the corresponding data line, and a control terminal that receives a connection control signal to control switching on and off, the display device including a function of measuring a drive current to be applied to each display element, the method comprising: a connection control step of controlling switching on and off of the plurality of connection control transistors; a data line driving step of applying the analog voltage signal to the second conduction terminal of each of the plurality of connection control transistors; a write control line driving step of selectively driving the plurality of write control lines; a monitor control line driving step of selectively driving a plurality of monitor control lines arrayed to correspond to each of the plurality of write control lines; and a voltage fluctuation compensation line driving step of selectively driving a plurality of voltage fluctuation compensation lines arrayed to correspond to each of the plurality of write control lines, wherein the display device includes a plurality of pixel circuits arranged in the matrix along the plurality of data lines and the plurality of write control lines, each pixel circuit corresponding to any one of the plurality of data lines and corresponding to any one of the plurality of write control lines, each pixel circuit includes: an electro-optical element as a display element with a brightness controlled by a current; a voltage holding capacitor that holds a data voltage controlling a drive current of the electro-optical element; an input transistor including a control terminal connected to a corresponding write control line, the input transistor being a switching element that controls a voltage supply from a corresponding data line to the voltage holding capacitor; a drive transistor that applies a drive current corresponding to the data voltage to the electro-optical element; a monitor control transistor including a control terminal connected to a monitor control line corresponding to the corresponding write control line, the monitor control transistor being arranged between the drive transistor and the corresponding data line to allow a current flowing through the drive transistor to pass through; a voltage fluctuation compensation transistor including a control terminal connected to a voltage fluctuation compensation line corresponding to the corresponding write control line and a first conduction terminal connected to the corresponding data line, the voltage fluctuation compensation transistor being connected in series to the monitor control transistor; and a voltage fluctuation compensation capacitor defined between the first conduction terminal in the voltage fluctuation compensation transistor and the control terminal in the voltage fluctuation compensation transistor, in the data line driving step, the analog voltage signal is output from each output terminal of a data line drive circuit including a predetermined number of output terminals respectively corresponding to a plurality of sets of data line groups obtained by grouping the plurality of data lines where one set includes a predetermined number of two or more data lines, each output terminal is connected to a second conduction terminal of a predetermined number of connection control transistors corresponding to a predetermined number of data lines of a corresponding set, in the connection control step, a predetermined number of connection control signals respectively corresponding to a predetermined number of data lines of each set are generated and the predetermined number of connection control signals are respectively applied to the control terminals of the predetermined number of connection control transistors corresponding to a predetermined number of data lines of each set to thereby successively switch on the predetermined number of connection control transistors of each set for each predetermined period in a first selection period during which any one of the plurality of write control lines is in a selected state, and in the voltage fluctuation compensation line driving step, in the first selection period, after the plurality of connection control transistors are changed from an on state to an off state, a voltage to be applied to a voltage fluctuation compensation line corresponding to a write control line in the selected state changes from a first voltage to a second voltage to thereby change a voltage of the corresponding voltage fluctuation compensation line in direction opposite to a change of a voltage to be applied to a control terminal of the plurality of connection control transistors to change the plurality of connection control transistors from an on state to an off state. ### Claim 10 (depends on 9) The driving method according to claim 9, further comprising: a current measurement step of measuring, via the plurality of data lines and the plurality of connection control transistors, a current flowing through a drive transistor in each pixel circuit, wherein, when measuring a drive current to be applied to a display element in a pixel circuit corresponding to any one write control line of the plurality of write control lines, in the monitor control line driving step, in a non-selection period, during the non-selection period the plurality of write control lines being in a non-selected state, the non-selection period occurring immediately after a second selection period, during the second selection period the one write control line being selected, the plurality of monitor control lines are driven to cause a monitor control transistor in the pixel circuit corresponding to the one write control line to be switched on, in the voltage fluctuation compensation line driving step, in the non-selection period, the plurality of voltage fluctuation compensation lines are driven to cause a voltage fluctuation compensation transistor in the pixel circuit corresponding to the one write control line to be switched on, in the connection control step, the predetermined number of connection control signals are respectively applied to the control terminals of the predetermined number of connection control transistors corresponding to a predetermined number of data lines of each set to thereby successively switch on the predetermined number of connection control transistors of each set for each predetermined period in the non-selection period, and in the current measurement step, a current flowing through a drive transistor in the pixel circuit corresponding to the one write control line is measured via a switched-on transistor out of the monitor control transistor, the voltage fluctuation compensation transistor, and the predetermined number of connection control transistors of each set.