# US 10,311,539 B2 · Task execution in a SIMD processing unit with parallel groups of processing lanes

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- Number: US 10,311,539 B2
- Document ID: US10311539B2
- Status: Granted
- Kind: B2
- Application number: 15/341,884
- Filed: 2016-11-02
- Published: 2017-03-16
- Granted: 2019-06-04
- Earliest claimed: 2013-12-18
- Assignees: Imagination Technologies Limited
- Applicants: Imagination Technologies Limited
- Inventors: John Howson; Jonathan Redshaw; Yoong Chert Foo
- Web page: https://patentgrep.com/patent/US10311539B2

## CPC

- G06T 1/20: Processor architectures; Processor configuration, e.g. pipelining
- G06F 9/30036: {Instructions to perform operations on packed data, e.g. vector, tile or matrix operations}
- G06F 9/30038: {using a mask}
- G06F 9/3822: {Parallel decoding, e.g. parallel decode units}
- G06F 9/3836: {Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution}
- G06F 9/3887: {controlled by a single instruction for multiple data lanes [SIMD]}
- G06F 9/38885: {Divergence aspects}
- G06F 15/8007: {single instruction multiple data [SIMD] multiprocessors}
- G06F 9/4881: {Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues}
- G06F 2209/507: Low-level
- G06T: IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.

## Claims

### Claim 1

A processing unit configured to process a plurality of tasks, wherein a task is arranged for executing a common sequence of instructions on each of a plurality of data items, the processing unit comprising:
a plurality of processing lanes divided into groups, each group being configured to execute instructions of a respective task over a plurality of processing cycles; and
a logic module configured to cause a particular group of processing lanes to skip a particular processing cycle, independently of the other groups of processing lanes, if there are no instructions scheduled for execution in any of the processing lanes of the particular group in the particular processing cycle even if there is at least one instruction scheduled for execution in the particular processing cycle in at least one of the processing lanes which is not in the particular group of processing lanes.

### Claim 2 (depends on 1)

The processing unit of claim 1 wherein the data items are arranged into blocks of data items, the number of data items in each of the blocks of data items being equal to the number of processing lanes in each of the groups of processing lanes, and wherein for each of the groups, in each of the plurality of processing cycles, the processing lanes of the group are configured to execute instructions relating to respective data items from a block of data items.

### Claim 3 (depends on 2)

The processing unit of claim 2 wherein the data items are pixel values and wherein the block of data items is a pixel quad.

### Claim 4 (depends on 1)

The processing unit of claim 1 wherein the data items are arranged into blocks of data items, and wherein for each of the groups, each of the processing lanes of the group is configured to execute instructions relating to a respective block of data items over a plurality of consecutive processing cycles.

### Claim 5 (depends on 4)

The processing unit of claim 4 wherein the data items are pixel values and wherein the respective block of data items is a pixel quad.

### Claim 6 (depends on 1)

The processing unit of claim 1 wherein the data items are pixel values, and wherein the processing unit is a SIMD processing unit.

### Claim 7 (depends on 1)

The processing unit of claim 1 wherein work items of a task are arranged for executing the common sequence of instructions for the task on respective data items for the task.

### Claim 8 (depends on 1)

The processing unit of claim 1 wherein each of the tasks includes up to a predetermined maximum number of work items.

### Claim 9 (depends on 8)

The processing unit of claim 8 wherein some of the tasks comprise fewer than the predetermined maximum number of work items.

### Claim 10 (depends on 1)

The processing unit of claim 1 wherein each of the groups of processing lanes is configured to execute instructions relating to a respective group of data items in a particular processing cycle.

### Claim 11 (depends on 1)

The processing unit of claim 1 wherein each of the groups of processing lanes comprises four processing lanes.

### Claim 12 (depends on 1)

The processing unit of claim 1 wherein the logic module is coupled to the groups of processing lanes.

### Claim 13

A method of using a processing unit to process a plurality of tasks, wherein a task is arranged for executing a common sequence of instructions on each of a plurality of data items, wherein the processing unit comprises a plurality of processing lanes divided into groups, the method comprising:
executing, at each group of processing lanes, instructions of a respective task over a plurality of processing cycles; and
causing a particular group of processing lanes to skip a particular processing cycle, independently of the other groups of processing lanes, if there are no instructions scheduled for execution in any of the processing lanes of the particular group in the particular processing cycle even if there is at least one instruction scheduled for execution in the particular processing cycle in at least one of the processing lanes which is not in the particular group of processing lanes.

### Claim 14 (depends on 13)

The method of claim 13 wherein the data items are arranged into blocks of data items, the number of data items in each of the blocks of data items being equal to the number of processing lanes in each of the groups of processing lanes, and wherein for each of the groups, in each of the plurality of processing cycles, the processing lanes of the group execute instructions relating to respective data items from a block of data items.

### Claim 15 (depends on 14)

The method of claim 14 wherein the data items are pixel values and wherein the block of data items is a pixel quad.

### Claim 16 (depends on 13)

The method of claim 13 wherein the data items are arranged into blocks of data items, and wherein for each of the groups, each of the processing lanes of the group executes instructions relating to a respective block of data items over a plurality of consecutive processing cycles.

### Claim 17 (depends on 13)

The method of claim 13 wherein work items of a task are arranged for executing the common sequence of instructions for the task on respective data items for the task, wherein each of the tasks includes up to a predetermined maximum number of work items, and wherein some of the tasks comprise fewer than the predetermined maximum number of work items.

### Claim 18 (depends on 13)

The method of claim 13 wherein each of the groups of processing lanes executes instructions relating to a respective group of data items in a particular processing cycle.

### Claim 19

A non-transitory computer readable storage medium having stored thereon processor executable instructions that when executed on at least one processor cause the generation of a processing unit which is configured to process a plurality of tasks, wherein a task is arranged for executing a common sequence of instructions on each of a plurality of data items, the processing unit comprising:
a plurality of processing lanes divided into groups, each group being configured to execute instructions of a respective task over a plurality of processing cycles; and
a logic module configured to cause a particular group of processing lanes to skip a particular processing cycle, independently of the other groups of processing lanes, if there are no instructions scheduled for execution in any of the processing lanes of the particular group in the particular processing cycle even if there is at least one instruction scheduled for execution in the particular processing cycle in at least one of the processing lanes which is not in the particular group of processing lanes.

### Claim 20 (depends on 1)

The processing unit of claim 1 wherein the data items are pixel values arranged into pixel quads, wherein each of the pixel quads is a 2×2 block of pixel values.