# US 10,311,226 B2 · Hacking-resistant computer design > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,226 B2 - Document ID: US10311226B2 - Status: Granted - Kind: B2 - Application number: 15/973,392 - Filed: 2018-05-07 - Published: 2018-11-15 - Granted: 2019-06-04 - Earliest claimed: 2015-08-31 - Assignees: Newman H-R Computer Design, LLC - Applicants: Newman H-R Computer Design, LLC - Inventors: Frank N. Newman; Dan Newman - Web page: https://patentgrep.com/patent/US10311226B2 ## CPC - G06F 21/50: Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems - G06F 3/0619: {in relation to data integrity, e.g. data losses, bit errors} - G06F 3/0644: {Management of space entities, e.g. partitions, extents, pools} - G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling} - G06F 12/1433: {for a module or a part of a module} - G06F 12/1441: {for a range} - G06F 21/53: by executing in a restricted environment, e.g. sandbox or secure virtual machine - G06F 21/71: to assure secure computing or processing of information - G06F 21/79: in semiconductor storage media, e.g. directly-addressable memories - H04L 63/10: {for controlling access to devices or network resources} - H04L 63/1441: {Countermeasures against malicious traffic (countermeasures against attacks on cryptographic mechanisms H04L9/002)} - H04L 63/145: {the attack involving the propagation of malware through the network, e.g. viruses, trojans or worms} - G06F 2212/1052: Security improvement - G06F 2221/031: Protect user input by software means - G06F 2221/032: Protect output to user by software means - G06F 2221/034: Test or assess a computer or a system - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract A computer architecture is disclosed for implementing a hacking-resistant computing device. The computing device, which could be a mainframe computer, personal computer, smartphone, or any other computing device suitable for network communication, comprises a first partition and a second partition. The second partition can communicate over a network such as the Internet. In contrast, the first partition cannot connect to the Internet, and can directly communicate only with the second partition or with input/output devices directly connected to the first partition. Further, the first partition segments its memory addressing for program code and hardware-protects it from alteration. The second partition is hardware-limited from reading or writing to the memory addressing of the first partition. As a result, the critical data files and program code stored on the first partition are protected from malicious code affecting the second partition. ## Claims ### Claim 1 A computer system comprising: a first partition and a second partition; the first partition comprising: a first CPU; and a first memory module comprising: at least one memory address range for program code, wherein the program code comprises computer-executable code, and wherein the at least one memory address range for program code is configured by hardware circuitry; and at least one memory address range for other data, wherein the other data comprises data read from the second partition; wherein the first CPU is hardware-configured to execute only the computer-executable code in the memory address range for program code; and the second partition comprising: a second CPU; a second memory module; and at least one communication module configured to couple to a network; wherein the first CPU is configured to access the second memory module and read data from the second partition into only the at least one memory address range for other data; and wherein the second CPU is restricted from accessing the first memory module. ### Claim 2 (depends on 1) The computer system of claim 1, wherein the first memory module comprises: a first memory unit comprising the at least one memory address range for program code; and a second memory unit comprising the at least one memory address range for other data. ### Claim 3 (depends on 1) The computer system of claim 1, wherein the at least one memory address range for other data comprises: at least one memory address range for data read from the second partition, and at least one memory address range for first partition data. ### Claim 4 (depends on 1) The computer system of claim 1, wherein the first memory module comprises: a first memory unit comprising the at least one memory address range for program code; a second memory unit for data read from the second partition; and a third memory unit for first partition data. ### Claim 5 (depends on 1) The computer system of claim 1, wherein the program code comprises an operating system, in whole or in part, including critical data used by the operating system. ### Claim 6 (depends on 1) The computer system of claim 1, wherein the first CPU is configured by hardware circuitry to access the second memory module; and wherein the second partition is restricted by hardware circuitry from accessing the first memory module. ### Claim 7 (depends on 1) The computer system of claim 1, wherein a hardware feature, utilizing an external device connected directly to the first partition, is configured to command the first CPU to take control of one or more input/output devices connected to the second partition. ### Claim 8 (depends on 1) The computer system of claim 1, further comprising a bus, wherein the first partition is interconnected to the second partition through the bus; wherein the first partition is configured to execute a pull command through the bus to read the data from the second partition and write the data only to the at least one memory address range for other data; wherein the first partition is configured to execute a push command through the bus to write data to the second partition; wherein the first partition is configured not to accept a push command from the second partition or a pull command from the second partition; and wherein the hardware circuitry of the bus does not permit the second partition to access the first memory module. ### Claim 9 (depends on 1) The computer system of claim 1, comprising at least one external physical switch configured to be turned on or off, wherein the first CPU is configured to modify data stored in the at least one memory address range for program code only when the external physical switch is on. ### Claim 10 (depends on 9) The computer system of claim 9, wherein identification data is stored in the memory address range for program code, and the identification data can be modified only when the at least one external physical switch is on. ### Claim 11 (depends on 1) The computer system of claim 1, comprising at least one data storage device. ### Claim 12 (depends on 1) The computer system of claim 1, wherein one or more chips comprise the first partition and the second partition. ### Claim 13 (depends on 1) The computer system of claim 1, wherein a hardware feature, utilizing an external device connected directly to the first partition, is configured to enable or disable the first CPU to write data to the second partition. ### Claim 14 (depends on 1) The computer system of claim 1, wherein: the first partition comprises one or more virtual sub-partitions; and the second partition comprises one or more virtual sub-partitions. ### Claim 15 (depends on 1) The computer system of claim 1, wherein the hardware circuitry comprises at least one field-programmable gate array. ### Claim 16 (depends on 1) The computer system of claim 1, wherein a server comprises the first partition and the second partition, and wherein the server holds critical files used by one or more other computers connected to the server. ### Claim 17 A computer system comprising: a first virtual partition and a second virtual partition; the first virtual partition comprising: a first CPU; and a first memory module comprising: at least one memory address range for program code, wherein the program code comprises computer-executable code; and at least one memory address range for other data, wherein the other data comprises data read from the second virtual partition; wherein the first CPU is configured to execute only the computer-executable code in the memory address range for program code; and the second virtual partition comprising: a second CPU; a second memory module; and at least one communication module configured to couple to a network; wherein the first CPU is configured to access by a virtual partition configuration the second memory module and read data from the second virtual partition into only the at least one memory address range for other data; and wherein the second CPU is restricted by a virtual partition configuration from accessing the first memory module. ### Claim 18 (depends on 17) The computer system of claim 17, wherein a virtual partition configuration is configured to turn on or off a restriction on writing to the at least one memory address range for program code. ### Claim 19 (depends on 17) The computer system of claim 17, comprising: a hardware feature comprising: at least one device connected to the first virtual partition; and an on position and an off position; wherein the first CPU cannot modify data in the at least one address range for program code unless the hardware feature is in the on position. ### Claim 20 (depends on 17) The computer system of claim 17, comprising: a hardware feature, comprising at least one device connected to the first virtual partition, and an on position and an off position, wherein the first CPU cannot modify data in the at least one address range for program code unless the hardware feature is in the on position; and wherein, while the at least one hardware feature is in the on position, the first CPU is disabled from accessing the second partition. ### Claim 21 (depends on 17) The computer system of claim 17, wherein a hardware feature, utilizing an external device connected directly to the first virtual partition, is configured to enable or disable the first CPU to write data to the second virtual partition. ### Claim 22 A computing device, comprising: a first connection to a first computer; a second connection to a second computer; wherein the computing device is configured to receive a pull command from the first computer and to execute the pull command to read data from the second computer through the computing device and write the data read from the second computer to at least one memory module of the first computer in a memory address range for data read from the second computer; wherein the computing device is configured to receive a push command from the first computer and to execute the push command to send data from the first computer to the second computer through the computing device; and wherein the computing device is configured to not permit a push command from the second computer to the first computer or a pull command from the second computer to the first computer; wherein the computing device is configured to not permit the second computer to access the at least one memory module of the first computer through the first connection and the second connection. ### Claim 23 (depends on 22) The computing device of claim 22, wherein the computing device comprises at least one memory module; wherein the data from the first computer and the data from the second computer is stored in the at least one memory module; wherein the computing device comprises at least one CPU; and wherein the push and pull commands received from the first computer are configured to be executed by a CPU of the computing device, reading data into the at least one memory module, and writing data from the at least one memory module. ### Claim 24 A computer system comprising: at least one CPU, at least one I/O module connecting to at least one other computer, and at least one memory module, comprising: at least one memory address range for program code, configured by hardware circuitry, wherein the program code comprises computer-executable code; at least one memory address range for other data, wherein the other data comprises data read from the at least one other computer; wherein the at least one CPU is hardware-configured to execute only the computer-executable code in the memory address range for program code; wherein data read from the at least one other computer can be written only into the at least one memory address range for other data; wherein the at least one memory module cannot be accessed by the at least one other computer. ### Claim 25 (depends on 24) The computer system of claim 24, wherein the at least one memory module comprises: a first memory unit for the at least one memory address range for program code; and a second memory unit for the at least one memory address range for other data. ### Claim 26 (depends on 24) The computer system of claim 24, wherein the memory addressing structure for program code is mapped by hardware circuitry comprising at least one field-programmable gate array. ### Claim 27 (depends on 24) The computer system of claim 24, comprising at least one external physical switch which can be turned on or off, wherein the first CPU can modify data stored in the at least one memory address range for program code only when the external physical switch is on. ### Claim 28 (depends on 24) The computer system of claim 24, further comprising: a bus, wherein the computer system is communicatively coupled to the at least one other computer through the bus; wherein the computer system is configured to execute a pull command through the bus to read the data from the at least one other computer and write the data only to the at least one memory address range for other data; wherein the computer system is configured to execute a push command through the bus to write data to the at least one other computer; wherein the computer system is configured not to accept a push command from the at least one other computer or a pull command from the at least one other computer; and wherein the hardware circuitry of the bus does not permit the at least one other computer to access the at least one memory module.