# US 10,311,196 B1 · Method and apparatus for performing symbolic timing analysis with spatial variation > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,196 B1 - Document ID: US10311196B1 - Status: Granted - Kind: B1 - Application number: 15/043,432 - Filed: 2016-02-12 - Granted: 2019-06-04 - Earliest claimed: 2016-02-12 - Assignees: Altera Corporation - Applicants: Altera Corporation - Inventors: David Lewis - Web page: https://patentgrep.com/patent/US10311196B1 ## CPC - G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) - G06F 30/3312: Timing analysis - G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] - G06F 30/343: Logical level - G06F 30/347: Physical level, e.g. placement or routing - G06F 30/392: Floor-planning or layout, e.g. partitioning or placement - G06F 2111/08: Probabilistic or stochastic CAD - G06F 2119/12: Timing analysis or timing optimisation - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A method for designing a system on a target device includes placing the system on the target device. Timing analysis is performed on the placed system to model delays by using a plurality of localized functions that overlap. ## Claims ### Claim 1 A method for designing a system on a target device, comprising: placing the system on the target device; performing timing analysis on the placed system to model delays by using a plurality of localized functions that overlap to represent an influence that affects a delay for an area on the target device that is a proper subset of a total area of the target device, wherein each of the plurality of localized functions cover less than a total area of the target device; generating a program file that includes a design of the system that is placed and timing analyzed; and programming the target device with the program file to transform programmable resources on the target device to implement the design, wherein the target device is implemented on an integrated circuit. ### Claim 2 (depends on 1) The method of claim 1, wherein the influence relates to process variation. ### Claim 3 (depends on 1) The method of claim 1, wherein the influence relates to a combination of process, temperature, and voltage variation on the target device. ### Claim 4 (depends on 1) The method of claim 1, wherein performing timing analysis comprises identifying the plurality of localized functions by defining a set of process variables, correlation distances, and magnitudes corresponding to variation on the target device. ### Claim 5 (depends on 1) The method of claim 1 further comprising identifying polynomial coefficients associated with a location on the target device by utilizing the localized functions. ### Claim 6 (depends on 5) The method of claim 5 further comprising removing delays that cannot form a minimum or maximum value. ### Claim 7 (depends on 5) The method of claim 5 further comprising: computing a root means square (RMS) of a difference of the delays; and removing polynomials that do not affect the RMS of the difference of the delays to a predetermined probability. ### Claim 8 (depends on 1) The method of claim 1, wherein the timing analysis is performed prior to routing. ### Claim 9 (depends on 1) The method of claim 1, wherein each of the plurality of localized functions are used together, collectively during the timing analysis. ### Claim 10 (depends on 1) The method of claim 1, wherein using the plurality of localized functions is performed prior to routing. ### Claim 11 (depends on 1) The method of claim 1 further comprising transmitting the program file to the target device. ### Claim 12 A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method for designing a system on a target device, comprising: placing the system on the target device; performing timing analysis on the placed system to model delays by using a plurality of localized functions that overlap to represent an influence that affects a delay for an area on the target device that is a proper subset of a total area of the target device, wherein each of the plurality of localized functions cover less than a total area of the target device; generating a program file that includes a design of the system that is placed and timing analyzed; and programming the target device with the program file to transform programmable resources on the target device to implement the design, wherein the target device is implemented on an integrated circuit. ### Claim 13 (depends on 12) The non-transitory computer readable medium of claim 12, wherein the influence relates to process variation. ### Claim 14 (depends on 12) The non-transitory computer readable medium of claim 12, wherein the influence relates to a combination of process, temperature, and voltage variation on the target device. ### Claim 15 (depends on 12) The non-transitory computer readable medium of claim 12, wherein performing timing analysis comprises identifying the plurality of localized functions by defining a set of process variables, correlation distances, and magnitudes corresponding to variation on the target device. ### Claim 16 (depends on 15) The non-transitory computer readable medium of claim 15 further comprising identifying polynomial coefficients associated with a location on the target device by utilizing the localized functions. ### Claim 17 (depends on 16) The non-transitory computer readable medium of claim 16 further comprising removing delays that cannot form a minimum or maximum value. ### Claim 18 (depends on 16) The non-transitory computer readable medium of claim 16 further comprising: computing a root means square (RMS) of a difference of the delays; and removing polynomials that do not affect the RMS of the difference of the delays to a predetermined probability. ### Claim 19 (depends on 12) The non-transitory computer readable medium of claim 12, wherein the timing analysis is performed prior to routing. ### Claim 20 A system designer, comprising: a placement unit that places a system on a target device; a timing analysis unit that performs timing analysis to model delay on the system that is placed by using a plurality of localized functions that overlap to represent an influence that affects a delay for an area on the target device that is a proper subset of a total area of the target device, wherein each of the plurality of localized functions cover less than a total area of the target device, and wherein at least one of the placement unit and the timing analysis unit is implemented by a processor; and an assembly unit that generates a data file that includes a design of the system that is placed and timing analyzed and programs the target device with the data file to transform programmable resources on the target device to implement the design, wherein the target device is implemented on an integrated circuit. ### Claim 21 (depends on 20) The system designer of claim 20, wherein the timing analysis unit comprises a localized function identifier that identifies the localized functions by defining a set of process variables, correlation distances, and magnitudes corresponding to variation on the target device. ### Claim 22 (depends on 20) The system designer of claim 20, wherein the timing analysis unit comprises a polynomial coefficients unit that identifies polynomial coefficients associated with a location on the target device by utilizing the localized functions. ### Claim 23 (depends on 20) The system designer of claim 20, wherein the timing analysis is performed prior to routing.