# US 10,311,194 B2 · Method of resolving multi-patterned color conflicts for multi-row logic cells

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- Number: US 10,311,194 B2
- Document ID: US10311194B2
- Status: Granted
- Kind: B2
- Application number: 14/828,496
- Filed: 2015-08-17
- Published: 2016-05-26
- Granted: 2019-06-04
- Earliest claimed: 2014-11-20
- Assignees: Samsung Electronics Co., Ltd.
- Applicants: Samsung Electronics Co., Ltd.
- Inventors: Andrew P. Hoover; Chandrakanth Ramesh; David A. Petermann
- Web page: https://patentgrep.com/patent/US10311194B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G03F 1/70: Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G03F: PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR; (phototypographic composing devices B41B; photosensitive materials or processes for photographic purposes G03C; electrophotography, sensitive layers or processes therefor G03G)

## Abstract

According to one general aspect, a method may include dividing circuit cells into colorable sub-portions, wherein each circuit cell includes one or more colorable sub-portions. The method may include determining if a violating colorable sub-portion is to be re-colored. The method may include indicating that the violating colorable sub-portion is to be at least partially re-colored.

## Claims

### Claim 1

A method of resolving circuit design rules, the method comprising:
accessing circuit cells from a cell library stored on a computer-readable medium;
creating new colorable sub-portions by dividing the circuit cells into colorable sub-portions, wherein each circuit cell is associated with one or more colorable sub-portions, and wherein multi-row circuit cells include a plurality of colorable sub-portions;
identifying a colorable sub-portion that violates a circuit design rule as a violating colorable sub-portion;
determining that the violating colorable sub-portion is to be re-colored;
creating a separate color swap layer, and indicating, via at least one shape of the color swap layer that the violating colorable sub-portion, but not the rest of the circuit cell, is to be at least partially re-colored, wherein re-coloring the sub-portion includes changing the color(s) of the colorable sub-portion without switching to another circuit cell; and
physically generating a lithographic mask based at least the re-colored sub-portion.

### Claim 2 (depends on 1)

The method of claim 1, wherein dividing includes dividing multi-row circuit cells into colorable sub-portions based, at least in part, upon row height.

### Claim 3 (depends on 2)

The method of claim 2, wherein determining includes iterating through colorable sub-portions by row, and
wherein if a multi-row circuit cell is encountered in a current row, iterating through all colorable sub-portions of the multi-row circuit cell within the current row and other colorable sub-portions of other circuit cells within the current row, before iterating through a colorable sub-portion of the multi-row circuit cell within a next row.

### Claim 4 (depends on 1)

The method of claim 1, wherein indicating includes altering a color swap layer shape that indicates to a mask generator that at least a layout portion of the circuit cell is to be re-associated from a first lithographic mask to a second lithographic mask.

### Claim 5 (depends on 4)

The method of claim 4, wherein at least one colorable sub-portion of the circuit cell is associated with a respective portion of the color swap layer.

### Claim 6 (depends on 1)

The method of claim 1, wherein a circuit cell includes a first colorable sub-portion and a second colorable sub-portion;
wherein determining includes determining that the first colorable sub-portion is to be re-colored and that the second colorable sub-portion is not to be re-colored; and
wherein indicating includes associating the first colorable sub-portion with a shape of a color swap layer, and not associating the second colorable sub-portion with any shape of the color swap layer.

### Claim 7 (depends on 1)

The method of claim 1, wherein indicating that the violating colorable sub-portion is to be at least partially re-colored occurs after a determination has been made for all circuit cells whether each of the circuit colorable sub-portions are to be re-colored.

### Claim 8 (depends on 1)

The method of claim 1, wherein indicating includes replacing a circuit cell associated with the violating colorable sub-portion with an at least partially re-colored version of the circuit cell.

### Claim 9 (depends on 1)

The method of claim 1, wherein dividing circuit cells into colorable sub-portions includes dividing the circuit cells into colorable sub-portions having variable widths and uniform heights.

### Claim 10

A method comprising:
receiving a circuit layout database that includes instantiations of circuit cells, wherein each instantiation includes one or more layout portions, wherein each layout portion is associated with a respective lithographic mask;
creating sub-portions of each instantiation of circuit cells by dividing the respective instantiations of the circuit cells into sub-portions of uniform height, wherein each instantiation includes one or more sub-portions;
evaluating if a design rule violation occurs between a first sub-portion and a second sub-portion;
determining if the design rule violation is to be corrected by re-associating one or more of the layout portions of the second sub-portion with a new lithographic mask;
if so, re-associating one or more of the layout portions of the second sub-portion with the new lithographic mask, wherein re-associating includes creating a color swap layer that identifies that the second sub-portion, and using at least in part the color swap layer, changing only the lithographic mask associated with the second sub-portion and not replacing the respective instantiation of the circuit cell with a new instantiation of the circuit cell; and
physically creating the new lithographic mask.

### Claim 11 (depends on 10)

The method of claim 10, wherein re-associating one or more of the layout portions of the second sub-portion with the new lithographic mask includes associating the layout portions with a color swap layer shape, wherein the color swap layer shape causes a mask generator to re-associate layout portions covered by the color swap layer shape with new lithographic masks.

### Claim 12 (depends on 10)

The method of claim 10, wherein organizing includes:
dividing a multi-row instantiation of a circuit cell into multiple sub-portions; and
organizing a single-row instantiation of a circuit cell into a single sub-portion.

### Claim 13 (depends on 10)

The method of claim 10, wherein evaluating includes iterating through sub-portions by row, and
wherein if a multi-row instantiation of a circuit cell is encountered in a current row, iterating through all sub-portions of the multi-row instantiation of the circuit cell within the current row and other sub-portions of other instantiations of other circuit cells within the current row, before iterating through a sub-portion of the multi-row instantiation of the circuit cell within a next row.

### Claim 14 (depends on 10)

The method of claim 10, wherein an instantiation of circuit cell includes a first sub-portion and a second sub-portion; and
wherein re-associating includes re-associating the first sub-portion with a new lithographic mask but maintaining an association between the second sub-portion with an original lithographic mask.

### Claim 15 (depends on 10)

The method of claim 10, wherein receiving includes:
placing a new instantiation of a circuit cell;
performing the organizing, evaluating, determining, and if determined, the re-associating steps of claim 10 for the new instantiation of a circuit cell; and
repeating the placing, organizing, evaluating, determining, and if determined, the re-associating steps for each desired instantiations of respective circuit cells until a circuit layout is complete.

### Claim 16 (depends on 10)

The method of claim 10, wherein re-associating includes replacing an instantiation of a first circuit cell associated with the second sub-portion with an instantiation of a second circuit cell, wherein the second circuit cell is functionally equivalent to the first circuit cell but is includes different associations with one or more lithographic masks.

### Claim 17 (depends on 10)

The method of claim 10, wherein evaluating includes measuring a distance between two layout portions that are associated with a common lithographic mask, and evaluating if the distance is greater than a threshold value.

### Claim 18

A system comprising:
a place and route tool configured to place instantiations of template circuit cells in a ordered pattern in a database of circuit layout;
a color checker tool configured to:
organize the instantiations by creating sub-portions from parts of respective instantiations of the template circuit cells, wherein each instantiation is associated with one or more sub-portions,
determine if color conflicts occur between neighboring sub-portions, and
create a separate color swap layer, and employ the color swap layer to indicate that a violating sub-portion, but not an entirety of an instantiation of the template circuit cells that is associated with the violating sub-portion, is to be re-colored, in whole or part, to correct a detected color conflict; and
a mask generator configured to:
physically generate at least two lithographic masks based upon a re-colored version of the circuit layout.

### Claim 19 (depends on 18)

The system of claim 18, wherein the color checker is configured to draw a shape, in a color swap layer, around at least a part of the violating sub-portion; and
wherein the mask generator is configured to dynamically re-associate one or more components enclosed by the shape in the color swap layer with an alternate lithographic mask.

### Claim 20 (depends on 18)

The system of claim 18, wherein the color checker is configured to replace, within the database of circuit layout, a violating instantiation that includes the violating sub-portion with an alternate instantiation that is functionally equivalent to the violating instantiation, but includes different associations with one or more lithographic masks.