# US 10,311,193 B2 · Alteration of a signal value for an FPGA at runtime

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- Number: US 10,311,193 B2
- Document ID: US10311193B2
- Status: Granted
- Kind: B2
- Application number: 14/823,197
- Filed: 2015-08-11
- Published: 2015-12-03
- Granted: 2019-06-04
- Earliest claimed: 2013-02-11
- Assignees: dSPACE digital signal processing and control engineering GmbH
- Applicants: dSPACE digital signal processing and control engineering GmbH
- Inventors: Heiko Kalte; Lukas Funke
- Web page: https://patentgrep.com/patent/US10311193B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/331: with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
- G06F 30/34: for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)

## Abstract

A method for changing a signal value of an FPGA at runtime, including the steps of loading an FPGA hardware configuration with at least one signal value onto the FPGA, running the FPGA hardware configuration on the FPGA, setting the signal value for transfer to the FPGA, determining writeback data from the signal value, writing the writeback data as status data to a configuration memory of the FPGA, and transferring the status data from the configuration memory to the functional level of the FPGA. A method is also provided for performing an FPGA build, including the steps of creating an FPGA hardware configuration with a plurality of signal values, arranging signal values in adjacent areas of the FPGA hardware configuration, ascertaining memory locations of a configuration memory for status data of the plurality of signal values on the basis of the FPGA hardware configuration, and creating a list containing signal values.

## Claims

### Claim 1

A method for changing a signal value of an FPGA at runtime, the method comprising:
loading an FPGA hardware configuration with at least one signal value onto the FPGA;
running the FPGA hardware configuration on the FPGA;
selecting at least one of the at least one signal value for transfer onto the FPGA on a control computer;
determining writeback data from the at least one signal value retrieved from the FPGA by the control computer;
writing the writeback data as status data in a configuration memory of the FPGA; and
transferring the status data from the configuration memory into a functional level of the FPGA as at least one altered signal value replacing the at least one signal value in the FPGA.

### Claim 2 (depends on 1)

The method according to claim 1, further comprising: before transferring the status data from the configuration memory into the functional level of the FPGA, transferring status data from the functional level of the FPGA into the configuration memory in a configuration level of the configuration memory.

### Claim 3 (depends on 1)

The method according to claim 1, wherein the step of determining the writeback data from the signal value includes the mapping of the signal value onto the writeback data.

### Claim 4 (depends on 1)

The method according to claim 1, wherein the step of writing the writeback data as the status data into the configuration memory of the FPGA includes determining areas of the configuration memory that are required for the change of the signal value and writing the status data of the required areas of the configuration memory as writeback data.

### Claim 5 (depends on 4)

The method according to claim 4, wherein the step of determination of areas of the configuration memory required to change the signal value, includes identification of respective areas via an identification number.

### Claim 6 (depends on 1)

The method according to claim 1, wherein the step of transferring the status data from the configuration memory into the functional plane of the FPGA includes determining components of the functional level of the FPGA necessary to write status data and transferring these components of status data into the functional level.

### Claim 7 (depends on 6)

The method according to claim 6, wherein the step of determination of components of the functional level of the FPGA, necessary for writing the status data, includes identification of components via an identification number.

### Claim 8 (depends on 7)

The method according to claim 7, wherein the step of determination of areas of the configuration memory required to change the signal value, includes identification of respective areas via an identification number.

### Claim 9 (depends on 1)

The method according to claim 1, wherein the step of selecting the signal value for transfer to the FPGA comprises providing a list of available signal values and the selection of a signal value from this list.

### Claim 10 (depends on 1)

The method according to claim 1, wherein the step of running the FPGA Hardware Configuration on the FPGA includes performing the hardware configuration as a real-time application, and wherein the method for changing a signal value of an FPGA is performed at runtime of the real-time application.

### Claim 11 (depends on 1)

The method according to claim 1, wherein the step of transferring the status data from the configuration memory into the functional level of the FPGA comprises sending a reset signal to the FPGA.

### Claim 12 (depends on 11)

The method according to claim 11, wherein the step of sending a reset signal to the FPGA includes sending a reset signal for the partial transfer of the status data from the configuration memory into the functional level of the FPGA.

### Claim 13 (depends on 1)

The method according to claim 1, the method further comprising:
creating the FPGA hardware configuration having at least two signal values, wherein memory locations of the status data of the signal values are adjacent to each other in the configuration memory;
determining memory locations in the configuration memory for the status data of the signal values based on the FPGA hardware configuration; and
creating a list of signal values accessible and/or changeable at runtime and of the memory locations of the signal values.

### Claim 14 (depends on 13)

The method according to claim 13, wherein the method further comprises implementing a reset signal for transferring status data from the configuration memory into the functional level of the FPGA, and wherein transfer of status data from the configuration memory into the functional level of the FPGA comprises a partial transfer of the status data from adjacent memory locations of the FPGA hardware configuration with the signal values.

### Claim 15 (depends on 1)

A data processing device with a processor unit and an FPGA, wherein the data processing device performs the method according to claim 1.

### Claim 16 (depends on 1)

A computer program product with computer-implemented prompts which after loading and running in a suitable data processing device performs the steps of the method according to claim 1.

### Claim 17 (depends on 1)

A digital storage medium with electronically readable control signals that are capable of cooperating with a data processing device such that the method is performed according to claim 1 on the data processing device.