# US 10,311,191 B2 · Memory including side-car arrays with irregular sized entries

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- Number: US 10,311,191 B2
- Document ID: US10311191B2
- Status: Granted
- Kind: B2
- Application number: 15/416,731
- Filed: 2017-01-26
- Published: 2018-07-26
- Granted: 2019-06-04
- Earliest claimed: 2017-01-26
- Assignees: Advanced Micro Devices, Inc.
- Applicants: Advanced Micro Devices, Inc.
- Inventors: John J. Wuu; Patrick J. Shyvers; Ryan Alan Selby
- Web page: https://patentgrep.com/patent/US10311191B2

## CPC

- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/394: Routing (G06F30/396 takes precedence)
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G11C 7/06: Sense amplifiers; Associated circuits {, e.g. timing or triggering circuits}
- G11C 7/20: Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
- G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)}
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)

## Abstract

A system and method for floorplanning a memory. A computing system includes a processing unit which generates memory access requests and a memory. The size of each memory line in the memory includes M bits. A memory macro block includes at least a primary array and a sidecar array. The primary array stores a first portion of a memory line and the sidecar array stores a second smaller portion of the memory line being accessed. The primary array and the sidecar array have different heights. The height of the sidecar array is based on a notch height in at least one corner of the memory macro block. The notch creates on-die space for s reserved area on the die. The notches result in cross-shaped, T-shaped, and/or L-shaped memory macro blocks.

## Claims

### Claim 1

A method of designing a memory, the method comprising:
generating layout data describing the memory, said generating comprising:
placing, by the computing system, a first portion of each memory line of the memory in a primary array of a memory macro block;
placing, by the computing system, a second portion of each memory line in a sidecar array of the memory macro block, wherein the second portion is smaller than the first portion;
determining, by the computing system, a height of the sidecar array based on a notch in the memory macro block corresponding to a reserved area, wherein the height of the sidecar array is less than a height of the primary array;
placing, by the computing system, the sidecar array in the memory macro block such that the notch is above or below the sidecar array when bit lines are oriented horizontally;
generating on one or more integrated circuit masks a description of the layout data.

### Claim 2 (depends on 1)

The method as recited in claim 1, wherein the reserved area is used for placement of one or more of a group of signal buffers, control logic, and a through silicon via with a corresponding keep out zone.

### Claim 3 (depends on 1)

The method as recited in claim 1, wherein each memory line in the memory comprises M bits, the second portion in the sidecar array comprises A bits of the M bits, a height of the reserved area comprises B bits, and the sidecar array has a number of entries equal to a number of entries in the primary array divided by an integer D, where D is a largest power-of-2 value less than or equal to a ratio of (M−A−B)/A.

### Claim 4 (depends on 3)

The method as recited in claim 3, further comprising:
placing the first portion of each memory line in the primary array with a bit separation S1; and
placing the second portion of each memory line in the sidecar array with a bit separation S2 equal to D times S1.

### Claim 5 (depends on 4)

The method as recited in claim 4, wherein the memory macro block further comprises a left bank and a right bank separated from one another, wherein the left bank includes a primary array and the right bank includes a sidecar array associated with the primary array in the left bank, and the right bank includes a primary array and the left bank includes a sidecar array associated with the primary array in the right bank.

### Claim 6 (depends on 5)

The method as recited in claim 5, wherein for at least one of the left bank and the right bank, the method further comprises routing a read line to be sensed by a sense amplifier to a first bit position of each first portion in the primary array and to a second bit position of each second portion in an unassociated sidecar array, wherein the second bit position is different from the first bit position.

### Claim 7 (depends on 6)

The method as recited in claim 6, wherein for at least one of the left bank and the right bank, the method further comprises routing each of the A bits in a sidecar array to selection logic and routing a set of D bits of the (M−A) bits in an unassociated primary array to the selection logic.

### Claim 8 (depends on 5)

The method as recited in claim 5, further comprising instantiating multiple copies of the memory macro block adjacent to one another, wherein at least one corner of each of the plurality of macro blocks comprises a notch providing on-die space for a reserved area.

### Claim 9 (depends on 5)

The method as recited in claim 5, wherein when creating a cross-shaped memory macro block, the method further comprises placing in each of the left bank and the right bank a sidecar array adjacent to an unassociated primary array with a notch above and below the sidecar array.

### Claim 10 (depends on 5)

The method as recited in claim 5, wherein the computing system comprises one of a design tool and a fabrication tool.

### Claim 11 (depends on 1)

The method as recited in claim 1, wherein a first bit line in the primary array and a second bit line in the sidecar array are a shared bit line for an access request, wherein the first bit line has a different number of bit lines above it than a number of bit lines above the second bit line and the first bit line has a different number of bit lines below it than a number of bit lines below the second bit line.

### Claim 12

A system for generating on one or more masks a layout of an integrated circuit, the system comprising:
a processor; and
a non-transitory computer readable medium storing instructions, the instructions when executed by the processor causing the system to:
generate layout data describing the integrated circuit, wherein to generate said layout the system is configured to:
place a first portion of each memory line of a memory in a primary array of a memory macro block;
place a second portion of each memory line in a sidecar array of the memory macro block, wherein the second portion is smaller than the first portion;
determine a height of the sidecar array based on a notch in the memory macro block corresponding to a reserved area, wherein the height of the sidecar array is less than a height of the primary array;
place the sidecar array in the memory macro block such that the notch is above or below the sidecar array when bit lines are oriented horizontally;
generate on one or more integrated circuit masks a description of the layout data.

### Claim 13 (depends on 12)

The system as recited in claim 12, wherein each memory line in the memory comprises M bits, the second portion in the sidecar array comprises A bits of the M bits, a height of the reserved area comprises B bits, and the sidecar array has a number of entries equal to a number of entries in the primary array divided by an integer D, where D is a largest power-of-2 value less than or equal to a ratio of (M−A−B)/A.

### Claim 14 (depends on 12)

The system as recited in claim 12, wherein the program instructions are further executable to:
place the first portion of each memory line in the primary array with a bit separation S1; and
place the second portion of each memory line in the sidecar array with a bit separation S2 equal to D times S1.

### Claim 15 (depends on 14)

The system as recited in claim 14, wherein the memory macro block further comprises a left bank and a right bank separated from one another, wherein the left bank includes a primary array and the right bank includes an associated sidecar array.

### Claim 16 (depends on 15)

The system as recited in claim 15, wherein for at least one of the left bank and the right bank, the program instructions are further executable to route a read line to be sensed by a sense amplifier to a first bit position of each first portion in the primary array and to a second bit position of each second portion in the unassociated sidecar array, wherein the second bit position is different from the first bit position.

### Claim 17

A computing system comprising:
a processing unit;
a memory comprising at least one memory macro block, wherein the at least one memory macro block comprises:
a primary array storing a first portion of each memory line of the memory;
a sidecar array storing a second portion of each memory line of the memory, wherein the second portion is smaller than the first portion;
wherein a height of the sidecar array is based on a notch in the memory macro block corresponding to a reserved area, wherein the height of the sidecar array is less than a height of the primary array; and
wherein the sidecar array is placed in the memory macro block such that the notch is above or below the sidecar array when bit lines are oriented horizontally; and
control logic, wherein in response to receiving an access request corresponding to a first memory line from the processing unit, the control logic is configured to access both a first entry of a first plurality of entries in the primary array and a second entry of a second plurality of entries in the sidecar array based on a same address in the received access request.

### Claim 18 (depends on 17)

The computing system as recited in claim 17, wherein each memory line in the memory comprises M bits, the second portion in the sidecar array comprises A bits of the M bits, a height of the reserved area comprises B bits, and the sidecar array has a number of entries equal to a number of entries in the primary array divided by an integer D, where D is a largest power-of-2 value less than or equal to a ratio of (M−A−B)/A.

### Claim 19 (depends on 18)

The computing system as recited in claim 18, wherein the primary array has a bit separation S1 and the sidecar array has a bit separation S2 equal to D times S1.

### Claim 20 (depends on 18)

The computing system as recited in claim 18, wherein the memory comprises a plurality of macro blocks, and wherein each of four corners of each of the plurality of memory macro blocks comprises a notch providing on-die space for the reserved area.