# US 10,311,190 B2 · Virtual hierarchical layer patterning

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- Number: US 10,311,190 B2
- Document ID: US10311190B2
- Status: Granted
- Kind: B2
- Application number: 15/654,511
- Filed: 2017-07-19
- Published: 2018-06-14
- Granted: 2019-06-04
- Earliest claimed: 2014-05-24
- Assignees: Synopsys, Inc.
- Applicants: Synopsys, Inc.
- Inventors: Jun Chen; James Lewis Nance; Gary B. Nifong
- Web page: https://patentgrep.com/patent/US10311190B2

## CPC

- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 30/00: Computer-aided design [CAD]
- G06F 30/20: Design optimisation, verification or simulation (optimisation, verification or simulation of circuit designs G06F30/30)
- G06F 30/392: Floor-planning or layout, e.g. partitioning or placement
- G06F 30/39: Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347)
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

Identifying the interactions of a selected cell across a hierarchical diagram of an integrated circuit and mapping the ways in which the cell can interact with other structures in the hierarchy reduces the computational load for design rule checking (DRC) and design rules for manufacturing (DRM). To this end, a cell and multiple instances of the cell are identified within hierarchical design levels of the chip. The interactions between the cell and other cells within the hierarchy are subtracted from the cell boundary, and the results of the subtracting are merged in the cell boundary. By subtracting the results of the merging, identical interactions are identified across the multiple instances of the cell. The results of the subtracting are used to generate a virtual hierarchical layer identical (VHLi) which aids in the simulation and verification of the chip.

## Claims

### Claim 1

A computer-implemented method for generating a layout of an integrated circuit design, the computer-implemented method comprising:
subtracting a first region defined by an overlap of a first polygon and a boundary of a first cell to form a modified first cell;
subtracting a second region defined by an overlap of a second polygon and a boundary of a second cell to form a modified second cell;
merging the modified first cell and the modified second cell to form a merged cell; and
subtracting the merged cell from the boundary of one of the first cell or the second cell to generate a virtual hierarchical layer used to form the layout of the integrated circuit design.

### Claim 2 (depends on 1)

The method of claim 1 wherein the boundary of the second cell is identical to the boundary of the first cell.

### Claim 3 (depends on 1)

The method of claim 1 further comprising verifying the layout using the virtual hierarchical layer.

### Claim 4 (depends on 1)

The method of claim 1 wherein the first and second cells and the first and second polygons are sibling cells of a parent cell.

### Claim 5 (depends on 1)

The method of claim 1 wherein the virtual hierarchical layer is defined by a first Boolean operation.

### Claim 6 (depends on 1)

The method of claim 1 wherein the merged cell is defined by a second Boolean operation.

### Claim 7

A computer system configured to generate a layout of an integrated circuit design, the computer system further configured to:
subtract a first region defined by an overlap of a first polygon and a boundary of a first cell to form a modified first cell;
subtract a second region defined by an overlap of a second polygon and a boundary of a second cell to form a modified second cell;
merge the modified first cell and the modified second cell to form a merged cell; and
subtract the merged cell from the boundary of one of the first cell or the second cell to generate a virtual hierarchical layer used to form the layout of the integrated circuit design.

### Claim 8 (depends on 7)

The computer system of claim 7 wherein the boundary of the second cell boundary is identical to the boundary of the first cell.

### Claim 9 (depends on 7)

The computer system of claim 7 wherein the computer system is further configured to verify the layout using the virtual hierarchical layer.

### Claim 10 (depends on 7)

The computer system of claim 7 wherein the first and second cells and the first and second polygons are sibling cells of a parent cell.

### Claim 11 (depends on 7)

The computer system of claim 7 wherein the virtual hierarchical layer is defined by a first Boolean operation.

### Claim 12 (depends on 7)

The computer system of claim 7 wherein the merged cell is defined by a second Boolean operation.