# US 10,311,186 B2 · Three-dimensional pattern risk scoring

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- Number: US 10,311,186 B2
- Document ID: US10311186B2
- Status: Granted
- Kind: B2
- Application number: 15/096,551
- Filed: 2016-04-12
- Published: 2017-10-12
- Granted: 2019-06-04
- Earliest claimed: 2016-04-12
- Assignees: Globalfoundries Inc.
- Applicants: GLOBALFOUNDRIES Inc.
- Inventors: Jaime Bravo; Vikrant Chauhan; Piyush Pathak; Shobhit Malik; Uwe Paul Schroeder
- Web page: https://patentgrep.com/patent/US10311186B2

## CPC

- G06F 30/367: Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
- G06F 30/398: Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36)
- G06F 2119/18: Manufacturability analysis or optimisation for manufacturability
- Y02P 90/02: Total factory control, e.g. smart factories, flexible manufacturing systems [FMS] or integrated manufacturing systems [IMS]
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- Y02P: CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS

## Abstract

Methodologies and a device for assessing integrated circuit and pattern for yield risk based on 3D simulation of semiconductor patterns are provided. Embodiments include generating, with a processor, a 3D simulation of semiconductor patterns; obtaining critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns; comparing the set of critical dimensions with predefined minimum dimensions; and yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step.

## Claims

### Claim 1

A method comprising:
generating, with a processor, a three dimensional (3D) simulation of semiconductor patterns;
obtaining a set of critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns;
comparing the set of critical dimensions with predefined minimum dimensions;
yield scoring, with non-linear models, each of the semiconductor patterns of the 3D simulation based on the comparing step;
generating an integrated circuit (IC) model based on the yield scoring each of the semiconductor patterns of the 3D simulation, the IC yield model including optimized parameters from design and process improvements,
wherein the 3D simulation of semiconductor patterns represents an actual process outcome on a wafer.

### Claim 2 (depends on 1)

The method according to claim 1, comprising:
normalizing an overall yield score to a volume of the 3D simulation of semiconductor patterns and translating into a risk factor.

### Claim 3 (depends on 2)

The method according to claim 2, wherein the risk factor is a direct measure of a yield probability of the IC model.

### Claim 4 (depends on 1)

The method according to claim 1, further comprising:
creating a two dimensional (2D) pattern risk assessment derived from the IC model for yield forecasting.

### Claim 5 (depends on 1)

The method of claim 1, further comprising:
identifying an at risk pattern prior to processing the IC model.

### Claim 6 (depends on 5)

The method according to claim 5, further comprising:
substituting the at risk pattern with an acceptable pattern, wherein the acceptable pattern has a lower risk factor than the at risk pattern.

### Claim 7 (depends on 1)

The method according to claim 1, comprising:
obtaining critical dimensions by obtaining a distance between adjacent conductors.

### Claim 8 (depends on 1)

The method according to claim 1, comprising:
obtaining critical dimensions by obtaining a distance between a tapered via and an adjacent metal line corner, wherein a minimum distance vector is angled in 3D space.

### Claim 9

A device comprising:
a three dimensional (3D) simulator that generates a 3D simulation of semiconductor patterns;
a processor configured to:
obtain a set of critical dimensions of distances between layers or within a layer of the 3D model of semiconductor patterns;
compare the set of critical dimensions with predefined minimum dimensions; and
yield score, with non-linear models, each of the semiconductor patterns of the 3D simulation based on the comparing step,
wherein the 3D simulation of semiconductor patterns represents an actual process outcome on a wafer,
yield score each of the semiconductor patterns of the 3D simulation to generate an integrated circuit (IC) model, and
wherein the IC yield model includes optimized parameters from design and process improvements.

### Claim 10 (depends on 9)

The device according to claim 9, wherein an overall yield score is normalized to a volume of the 3D simulation of semiconductor patterns and translated into a risk factor.

### Claim 11 (depends on 10)

The device according to claim 10, wherein the risk factor is a direct measure of a yield probability of the IC model.

### Claim 12 (depends on 9)

The device according to claim 9, wherein the processor is further configured to:
create a two dimensional (2D) pattern risk assessment derived from the IC model for yield forecasting.

### Claim 13 (depends on 9)

The device according to claim 9, wherein the processor is further configured to:
identify an at risk pattern prior to processing the IC model; and
substitute the at risk pattern with an acceptable pattern,
wherein the acceptable pattern has a lower risk factor than the at risk pattern.

### Claim 14

A method comprising:
generating, with a processor, a three dimensional (3D) simulation of semiconductor patterns representing an actual process outcome on a wafer;
obtaining a set of critical dimensions of distances between layers or within a layer of the 3D simulation of semiconductor patterns;
comparing the set of critical dimensions with predefined minimum dimensions;
yield scoring each of the semiconductor patterns of the 3D simulation based on the comparing step to generate an integrated circuit (IC) model;
normalizing an overall yield score to a volume of the 3D simulation of semiconductor patterns and translating it into a risk factor;
identifying an at risk pattern prior to processing the IC model; and
substituting the at risk pattern with an acceptable pattern,
wherein the acceptable pattern has a lower risk factor than the at risk pattern,
wherein the risk factor is a direct measure of a yield probability of the IC model, and
wherein the 3D simulation of semiconductor patterns represents the actual process outcome on the wafer.