# US 10,311,126 B2 · Memory device for matrix-vector multiplications > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,126 B2 - Document ID: US10311126B2 - Status: Granted - Kind: B2 - Application number: 15/235,157 - Filed: 2016-08-12 - Published: 2018-02-15 - Granted: 2019-06-04 - Earliest claimed: 2016-08-12 - Assignees: International Business Machines Corporation - Applicants: International Business Machines Corporation - Inventors: Manuel Le Gallo; Abu Sebastian - Web page: https://patentgrep.com/patent/US10311126B2 ## CPC - G06F 17/16: Matrix or vector computation {, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization (matrix transposition G06F7/78)} - G11C 11/16: using elements in which the storage effect is based on magnetic spin effect - G11C 11/56: using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency - G11C 11/5607: {using magnetic storage elements} - G11C 11/5614: {using conductive bridging RAM [CBRAM] or programming metallization cells [PMC]} - G11C 11/5678: {using amorphous/crystalline phase transition storage elements} - G11C 11/5685: {using storage elements comprising metal oxide memory material, e.g. perovskites} - G11C 13/0002: {using resistive RAM [RRAM] elements} - G11C 13/0004: {comprising amorphous/crystalline phase transition cells} - G11C 13/0007: {comprising metal oxide memory material, e.g. perovskites} - G11C 13/0011: {comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]} - G11C 13/004: {Reading or sensing circuits or methods} - G11C 13/0069: {Writing or programming circuits or methods} - G11C 13/04: using optical elements {; using other beam accessed elements, e.g. electron or ion beam} - G11C 13/047: {using electro-optical elements (G11C13/042 takes precedence)} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A device for performing a multiplication of a matrix with a vector. The device comprises a plurality of memory elements, a signal generator and a readout circuit. The signal generator is configured to apply programming signals to the memory elements. The signal generator is further configured to control a first signal parameter of the programming signals in dependence on matrix elements of the matrix and to control a second signal parameter of the programming signals in dependence on vector elements of the vector. The readout circuit is configured to read out memory values of the memory elements. The memory values represent result values of vector elements of a product vector of the multiplication. The memory elements may be in particular resistive memory elements or photonic memory elements. Additionally there is provided a related method and design structure for performing the multiplication of a matrix with a vector. ## Claims ### Claim 1 A device for performing a multiplication of a matrix with a vector, the device comprising: a plurality of memory elements; a signal generator configured to apply programming signals to the memory elements; control a first signal parameter of the programming signals in dependence on matrix elements of the matrix; and control a second signal parameter of the programming signals in dependence on vector elements of the vector; and a readout circuit configured to read out memory values of the memory elements, the memory values representing result values of vector elements of a product vector of the multiplication, wherein the device is configured to perform multiple runs for the multiplication and to perform an averaging of result values of the multiple runs. ### Claim 2 (depends on 1) The device according to claim 1, wherein the device comprises an array of memory elements and wherein the device is configured to provide a memory element for each vector element of the product vector. ### Claim 3 (depends on 2) The device as claimed in claim 2, wherein the device comprises an array of input terminals configured to convey an input signal to the memory elements; and an array of transistors arranged in series to the memory elements; wherein the signal generator is configured to control a control signal of a control terminal of the transistors. ### Claim 4 (depends on 1) The device according to claim 1, wherein the device is configured to perform the multiplication by a plurality of successive steps in an accumulative manner; and perform at each of the successive steps simultaneously a multiplication of column elements of one of the columns of the matrix with a corresponding vector element of the vector. ### Claim 5 (depends on 1) The device according to claim 1, wherein the signal generator is a pulse generator configured to apply pulses to the memory elements and wherein the first signal parameter is a first pulse parameter and the second signal parameter is a second pulse parameter. ### Claim 6 (depends on 5) The device according to claim 5, wherein the first pulse parameter is a duration of the pulses. ### Claim 7 (depends on 5) The device according to claim 5, wherein the second pulse parameter is an amplitude of the pulses. ### Claim 8 (depends on 5) The device according to claim 5, wherein the second pulse parameter is a number of the pulses. ### Claim 9 (depends on 1) The device as claimed in claim 1, wherein the memory elements are resistive memory elements; the programming signals are electrical programming signals; and the memory values are resistance values. ### Claim 10 (depends on 9) The device as claimed in claim 9, wherein the resistive memory elements are one of Phase change memory (PCM) elements, Conductive bridge resistive memory elements, Metal-oxide resistive random access memory (RRAM) elements and Magneto-resistive random access memory (MRAM) elements. ### Claim 11 (depends on 9) The device as claimed in claim 9, wherein the resistive memory elements are Phase change memory elements and wherein the device is configured to: apply a Reset-pulse to the PCM elements in order to bring the PCM-elements in the amorphous state; apply current pulses to the PCM elements that heat the PCM elements above the crystallization temperature, thereby lowering the resistance of the PCM elements. ### Claim 12 (depends on 9) The device according to claim 9, wherein the resistive memory elements are phase change memory elements; the device comprises an array of counters; and the device is configured to: detect a predefined low resistance state of the resistive memory elements; send an intermediate result value of a pending multiplication to a counter allocated to the respective resistive memory element having the low resistance state; and apply a reset pulse to the respective resistive memory element having the low resistance state. ### Claim 13 (depends on 12) The device according to claim 12, wherein the result values of the vector elements of the product vector are represented by counter values of the counter. ### Claim 14 (depends on 1) The device as claimed in claim 1, wherein the memory elements are photonic memory elements; the programming signals are optical programming signals; and the memory values are optical absorption values. ### Claim 15 A method for performing a matrix multiplication of a matrix with a vector, the method comprising: applying, by a signal generator, programming signals to a plurality of memory elements; controlling a first signal parameter of the programming signals in dependence on matrix elements of the matrix; controlling a second signal parameter of the programming signals in dependence on vector elements of the vector; and reading out, by a readout circuit, memory values of the memory elements, the memory values representing result values of vector elements of a product vector of the multiplication; the method further comprising: performing multiple runs for the multiplication; and performing an averaging of result values of the multiple runs. ### Claim 16 (depends on 15) The method according to claim 15, wherein the method further comprises performing the multiplication by a plurality of successive steps in an accumulative manner; and performing at each of the successive steps simultaneously a multiplication of column elements of one of the columns of the matrix with a corresponding vector element of the vector. ### Claim 17 (depends on 15) The method according to claim 15, wherein the memory elements are resistive memory elements and the resistive memory elements are phase change memory elements and wherein the method further comprises: detecting a predefined low resistance state of the resistive memory elements; sending an intermediate result value of a pending multiplication to a counter allocated to the respective resistive memory element having the low resistance state; and applying a reset pulse to the respective resistive memory element having the low resistance state. ### Claim 18 A design structure tangibly embodied in a non-transitory machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure comprising: a device for performing a multiplication of a matrix with a vector comprising a plurality of memory elements; a signal generator configured to apply programming signals to the memory elements; control a first signal parameter of the programming signals in dependence on matrix elements of the matrix; and control a second signal parameter of the programming signals in dependence on vector elements of the vector; and a readout circuit configured to read out memory values of the memory elements, the memory values representing result values of vector elements of a product vector of the multiplication, wherein the device is configured to perform multiple runs for the multiplication and to perform an averaging of result values of the multiple runs.