# US 10,311,005 B2 · Message translator > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 10,311,005 B2 - Document ID: US10311005B2 - Status: Granted - Kind: B2 - Application number: 15/130,656 - Filed: 2016-04-15 - Published: 2017-10-19 - Granted: 2019-06-04 - Earliest claimed: 2016-04-15 - Assignees: Atmel Corporation - Applicants: Atmel Corporation - Inventors: Kerry Maletsky; Nicolas Schieli; Timothy Grai - Web page: https://patentgrep.com/patent/US10311005B2 ## CPC - G06F 13/4027: {using bus bridges (G06F13/4022 takes precedence)} - G06F 13/4221: {being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus} - H04L 12/40013: {Details regarding a bus controller} - H04L 2012/40215: {Controller Area Network CAN} - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) - H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M) ## Abstract Systems, methods, circuits and computer-readable mediums for a network message translator are disclosed. In an embodiment, a device includes a host processor and a translator. The host processor is configured to process messages and the translator is operable to: receive a first message from the host processor, the first message having a first frame format that is associated with a data time window; translate the first message into a first translated message having a second frame format such that the first translated message includes additional bits based on the second frame format; and sending the first translated message on a bus based on the second frame format such that the first translated message is sent on the bus during the data time window. ## Claims ### Claim 1 A device comprising: a host processor configured to process messages for transmission on a data bus; a translator coupled to the data bus and configured to: receive a message frame from the host processor over an interface, the message frame having a first frame format that is configured to be transmitted on the data bus within a data time window at a first data rate; translate the message frame into a translated message frame having a second frame format, the second frame format including data bits representing a message, sequence bits representing a binary counter to a prevent relay attack, pad bits to fill out the translated message frame and allow bit alignment and security bits to detect if the data bits were modified between transmitting and receiving nodes coupled to the data bus by an unauthorized transmitter coupled to the data bus, the second frame format configured to be transmitted on the data bus within the data time window at a second data rate higher than the first data rate; and during the data time window, placing the data bits on the data bus, followed by the sequence bits, followed by a first portion of the pad bits, followed by the security bits, followed by a second portion of the pad bits. ### Claim 2 (depends on 1) The device of claim 1, wherein at least one of the sequence bits and the pad bits are placed on the data bus while at least one of the data bits is being received by the translator from the host processor across the interface. ### Claim 3 (depends on 1) The device of claim 1, wherein at least one of the security bits and error code bits in the translated message frame are placed on the data bus during an error code time window of the message frame. ### Claim 4 (depends on 1) The device of claim 1, wherein the data bus is a Controller Area Network (CAN) bus. ### Claim 5 (depends on 1) The device of claim 1, wherein the device is further configured to: prior to transmitting the data bits on the data bus: transfer the data bits to the translator; and compute, by the translator, the security bits based on the data bits. ### Claim 6 (depends on 1) The device of claim 1, wherein the translator is integrated with a bus transceiver. ### Claim 7 (depends on 1) The device of claim 1, wherein the security bits comprise a message authentication code (MAC). ### Claim 8 A non-transitory, computer-readable storage medium having instructions stored thereon, which, when executed by one or more processors, causes the one or more processors to perform operations comprising: receiving a message frame from the host processor over an interface, the message frame having a first frame format that is configured to be transmitted on a data bus within a data time window at a first data rate; translating the message frame into a translated message frame having a second frame format, the second frame format including data bits representing a message, sequence bits representing a binary counter to a prevent relay attack, pad bits to fill out the translated message frame and allow bit alignment and security bits to detect if the data bits were modified between transmitting and receiving nodes coupled to the data bus by an unauthorized transmitter coupled to the data bus, the second frame format configured to be transmitted on the data bus within the data time window at a second data rate higher than the first data rate; and during the data time window, placing the data bits on the data bus, followed by the sequence bits, followed by a first portion of the pad bits, followed by the security bits, followed by a second portion of the pad bits. ### Claim 9 (depends on 8) The computer-readable storage medium of claim 8, wherein at least one of the sequence bits and the pad bits are placed on the data bus while at least one of the data bits are being received by the translator from the host processor across the interface. ### Claim 10 (depends on 8) The computer-readable storage medium of claim 8, wherein at least one of the security bits and error code bits in the translated message frame are placed on the data bus during an error code time window of the message frame. ### Claim 11 (depends on 8) The computer-readable storage medium of claim 8, wherein the data bus is a Controller Area Network (CAN) bus. ### Claim 12 (depends on 8) The computer-readable storage medium of claim 8, wherein prior to transmitting the data bits on the data bus: transferring the data bits to the translator; and computing, by the translator, the security bits based on the data bits. ### Claim 13 (depends on 8) The computer-readable storage medium of claim 8, wherein the security bits comprise a message authentication code (MAC). ### Claim 14 A method comprising: receiving a message frame from the host processor over an interface, the message frame having a first frame format that is configured to be transmitted on a data bus within a data time window at a first data rate; translating the message frame into a translated message frame having a second frame format, the second frame format including data bits representing a message, sequence bits representing a binary counter to a prevent relay attack, pad bits to fill out the translated message frame and allow bit alignment and security bits to detect if the data bits were modified between transmitting and receiving nodes coupled to the data bus by an unauthorized transmitter coupled to the data bus, the second frame format configured to be transmitted on the data bus within the data time window at a second data rate higher than the first data rate; and during the data time window, placing the data bits on the data bus, followed by the sequence bits, followed by a first portion of the pad bits, followed by the security bits, followed by a second portion of the pad bits. ### Claim 15 (depends on 14) The method of claim 14, wherein the data bus is a Controller Area Network (CAN) bus. ### Claim 16 (depends on 14) The method of claim 14, wherein the security bits comprise a message authentication code (MAC). ### Claim 17 (depends on 14) The method of claim 14, wherein at least one of the sequence bits and the pad bits are placed on the data bus while at least one of the data bits are being received by the translator from the host processor across the interface. ### Claim 18 (depends on 14) The method of claim 14, wherein at least one of the security bits and error code bits in the translated message frame are placed on the data bus during an error code time window of the message frame. ### Claim 19 (depends on 14) The method of claim 14, further comprising: transferring the data bits to the translator; and computing, by the translator, the security bits based on the data bits. ### Claim 20 (depends on 19) The method of claim 19, further comprising: caching, by the translator, the data bits; and synchronizing, by the translator, the data bits in the message frame and translated message frame by matching control fields in the message frame and the translated method frame.