# US 10,310,999 B2 · Flash memory controller with calibrated data communication

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- Number: US 10,310,999 B2
- Document ID: US10310999B2
- Status: Granted
- Kind: B2
- Application number: 15/702,987
- Filed: 2017-09-13
- Published: 2018-04-05
- Granted: 2019-06-04
- Earliest claimed: 1999-10-19
- Applicants: Rambus Inc.
- Inventors: Jared LeVan Zerbe; Kevin S. Donnelly; Stefanos Sidiropoulos; Donald C. Stark; Mark A. Horowitz; Leung Yu; Roxanne Vu; Jun Kim; Bruno W. Garlepp; Tsyr-Chyang Ho; Benedict Chung-Kwong Lau
- Web page: https://patentgrep.com/patent/US10310999B2

## CPC

- G06F 13/364: using independent requests or grants, e.g. using separated request and grant lines
- G06F 1/10: Distribution of clock signals {, e.g. skew}
- G06F 3/061: {Improving I/O performance}
- G06F 3/0659: {Command handling arrangements, e.g. command buffers, queues, command scheduling}
- G06F 3/0679: {Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]}
- G06F 12/0246: {in block erasable memory, e.g. flash memory}
- G06F 13/1689: {Synchronisation and timing concerns (synchronisation on a memory bus G06F13/4234)}
- G06F 13/1694: {Configuration of memory controller to different memory types}
- G06F 13/404: {with address mapping}
- G06F 13/4243: {with synchronous protocol}
- G06F 13/4282: {on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247)}
- G11C 7/1045: {Read-write mode select circuits}
- H04L 7/0008: {Synchronisation information channels, e.g. clock distribution lines}
- G06F 2212/7201: Logical to physical mapping or translation of blocks or pages
- G06F 2212/7207: management of metadata or control data
- H04L 7/033: using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N)
- G11C: STATIC STORES (semiconductor memory devices H10B)
- H04L: TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION (arrangements common to telegraphic and telephonic communication H04M)

## Abstract

An integrated circuit device includes a transmitter circuit operable to transmit a timing signal over a first wire to a DRAM. The DRAM receives a first signal having a balanced number of logical zero-to-one transitions and one-to-zero transitions and samples the first signal at a rising edge of the timing signal to produce a respective sampled value. The device further includes a receiver circuit to receive the respective sampled value from the DRAM over a plurality of wires separate from the first wire. In a first mode, the transmitter circuit repeatedly transmits incrementally offset versions of the timing signal to the DRAM until sampled values received from the DRAM change from a logical zero to a logical one or vice versa; and in a second mode, it transmits write data over the plurality of wires to the DRAM according to a write timing offset generated based on the sampled values.

## Claims

### Claim 1

A flash memory device comprising:
a register to store a value, wherein the value is used by the flash memory device to control a reference voltage; and
a receiver circuit to receive data using the reference voltage as controlled in accordance with the value.

### Claim 2 (depends on 1)

The flash memory device of claim 1 further comprising:
an input to receive a first device identification signal; and
an output to transmit a second device identification signal.

### Claim 3 (depends on 1)

The flash memory device of claim 1, wherein the register stores the value in response to a calibration operation.

### Claim 4 (depends on 1)

The flash memory device of claim 1 further comprising:
an output driver to transmit data in response to a read command; and
a register to store a value representative of a drive strength of the output driver.

### Claim 5 (depends on 1)

The flash memory device of claim 1 wherein:
the receiver circuit is to receive a device identifier identifying the flash memory device for an operation; and
the receiver circuit is to receive an opcode identifying the operation to be performed by the flash memory device, the operation including a write operation of the data.

### Claim 6 (depends on 1)

The flash memory device of claim 1 wherein the receiver circuit stores the value as a result of a calibration operation.

### Claim 7 (depends on 1)

The flash memory device of claim 1 further comprising a pin to receive an external voltage, wherein the value to set the reference voltage specifies using the external voltage to set the reference voltage.

### Claim 8 (depends on 7)

The flash memory device of claim 7, wherein the value used by the flash memory device to set the reference voltage specifies an offset between the external voltage and the reference voltage used by the receiver circuit.

### Claim 9

A method of operation of a flash memory device, the method comprising:
receiving a value, wherein the value is used by the flash memory device to set a reference voltage;
storing the value in a register; and
during operation, receiving data using the reference voltage as set in accordance with the value.

### Claim 10 (depends on 9)

The method of claim 9, further comprising:
receiving a device identifier identifying the individual flash memory device; and
receiving an opcode identifying an operation to be performed by the individual flash memory device.

### Claim 11 (depends on 9)

The method of claim 9 further comprising:
storing a value representative of a drive strength setting of the output driver of the flash memory device; and
transmitting data using the drive strength setting.

### Claim 12 (depends on 9)

The method of claim 9 further comprising:
receiving a device identifier identifying the flash memory device for an operation; and
receiving an opcode identifying the operation to be performed by the flash memory device, the operation including a write operation of the data.

### Claim 13 (depends on 9)

The method of claim 9 further comprising storing the value as a result of a calibration operation.

### Claim 14 (depends on 9)

The method of claim 9 further comprising receiving an external voltage, wherein the value to set the reference voltage specifies using the external voltage to set the reference voltage used to receive the data.

### Claim 15 (depends on 14)

The method of claim 14, wherein the value used by the flash memory device to set the reference voltage specifies an offset between the external voltage and the reference voltage used to receive the data.

### Claim 16

A flash memory device comprising:
means for storing a value, wherein the value is used by the flash memory device to control a reference voltage; and
means for receiving data using the reference voltage as controlled in accordance with the value.

### Claim 17 (depends on 16)

The flash memory device of claim 16 further comprising:
an input to receive a first device identification signal; and
an output to transmit a second device identification signal.

### Claim 18 (depends on 16)

The flash memory device of claim 16, wherein means for storing receives the value in response to a calibration operation.

### Claim 19 (depends on 16)

The flash memory device of claim 16 further comprising:
an output driver to transmit data in response to a read command; and
a register to store a value representative of a drive strength of the output driver.

### Claim 20 (depends on 16)

The flash memory device of claim 16 wherein:
the means for receiving data is to receive a device identifier identifying the flash memory device for an operation; and
the means for receiving data is to receive an opcode identifying the operation to be performed by the flash memory device, the operation including a write operation of the data.